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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id gt10sm5443755pjb.30.2020.05.21.19.35.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 May 2020 19:35:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 16/25] Split out recv_register_info Date: Thu, 21 May 2020 19:34:31 -0700 Message-Id: <20200522023440.26261-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200522023440.26261-1-richard.henderson@linaro.org> References: <20200522023440.26261-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will want to share this code when dumping. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- risu.c | 50 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 34 insertions(+), 16 deletions(-) -- 2.20.1 diff --git a/risu.c b/risu.c index b91ad38..80bc3b1 100644 --- a/risu.c +++ b/risu.c @@ -166,6 +166,34 @@ static void master_sigill(int sig, siginfo_t *si, void *uc) } } +static RisuResult recv_register_info(struct reginfo *ri) +{ + RisuResult res; + + res = read_buffer(&header, sizeof(header)); + if (res != RES_OK) { + return res; + } + + /* send OK for the header */ + respond(RES_OK); + + switch (header.risu_op) { + case OP_COMPARE: + case OP_TESTEND: + case OP_SIGILL: + return read_buffer(ri, reginfo_size()); + case OP_COMPAREMEM: + return read_buffer(other_memblock, MEMBLOCKLEN); + case OP_SETMEMBLOCK: + case OP_GETMEMBLOCK: + return RES_OK; + default: + /* TODO: Create a better error message. */ + return RES_BAD_IO; + } +} + static RisuResult recv_and_compare_register_info(void *uc) { uint64_t paramreg; @@ -173,33 +201,26 @@ static RisuResult recv_and_compare_register_info(void *uc) RisuOp op; reginfo_init(&ri[APPRENTICE], uc); - op = get_risuop(&ri[APPRENTICE]); - res = read_buffer(&header, sizeof(header)); + res = recv_register_info(&ri[MASTER]); if (res != RES_OK) { + /* I/O error. Tell master to exit. */ + respond(RES_END); return res; } + op = get_risuop(&ri[APPRENTICE]); if (header.risu_op != op) { /* We are out of sync. Tell master to exit. */ respond(RES_END); return RES_BAD_IO; } - /* send OK for the header */ - respond(RES_OK); - switch (op) { case OP_COMPARE: case OP_TESTEND: case OP_SIGILL: - /* Do a simple register compare on (a) explicit request - * (b) end of test (c) a non-risuop UNDEF - */ - res = read_buffer(&ri[MASTER], reginfo_size()); - if (res != RES_OK) { - /* fail */ - } else if (!reginfo_is_eq(&ri[MASTER], &ri[APPRENTICE])) { + if (!reginfo_is_eq(&ri[MASTER], &ri[APPRENTICE])) { /* register mismatch */ res = RES_MISMATCH_REG; } else if (op == OP_TESTEND) { @@ -216,10 +237,7 @@ static RisuResult recv_and_compare_register_info(void *uc) set_ucontext_paramreg(uc, paramreg + (uintptr_t)memblock); break; case OP_COMPAREMEM: - res = read_buffer(other_memblock, MEMBLOCKLEN); - if (res != RES_OK) { - /* fail */ - } else if (memcmp(memblock, other_memblock, MEMBLOCKLEN) != 0) { + if (memcmp(memblock, other_memblock, MEMBLOCKLEN) != 0) { /* memory mismatch */ res = RES_MISMATCH_MEM; }