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d="scan'208";a="136507035" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 30 Apr 2020 04:28:38 +0800 IronPort-SDR: CeRKygex5l3tRKGpoVTJ/HpyKXe5KVGrN76WAEhMgXp4l5hU0YsRMKy9p74fM8x9AVk59JChUA LL52X7LIV6Azw7uZ2noEq/9DN4faDP3eY= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2020 13:18:43 -0700 IronPort-SDR: sDB1xR12VpedGS0KGRXXFsa7kDST6+JO5JZ6D7vssW1rYxOyX7agMMNvEN1UYa/alHj40g8RF5 ns7s0+s+RTzQ== WDCIronportException: Internal Received: from usa004631.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.56.145]) by uls-op-cesaip01.wdc.com with ESMTP; 29 Apr 2020 13:28:38 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 05/14] riscv: AND stage-1 and stage-2 protection flags Date: Wed, 29 Apr 2020 13:19:57 -0700 Message-Id: <20200429202006.775322-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429202006.775322-1-alistair.francis@wdc.com> References: <20200429202006.775322-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=381fbd49e=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/29 16:28:37 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , palmerdabbelt@google.com, Richard Henderson , qemu-devel@nongnu.org, Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Take the result of stage-1 and stage-2 page table walks and AND the two protection flags together. This way we require both to set permissions instead of just stage-2. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Tested-by: Anup Patel Message-id: 846f1e18f5922d818bc464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com Message-Id: <846f1e18f5922d818bc464ec32c144ef314ec724.1585262586.git.alistair.francis@wdc.com> --- target/riscv/cpu_helper.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f36d184b7b..50e13a064f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -707,7 +707,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, #ifndef CONFIG_USER_ONLY vaddr im_address; hwaddr pa = 0; - int prot; + int prot, prot2; bool pmp_violation = false; bool m_mode_two_stage = false; bool hs_mode_two_stage = false; @@ -757,13 +757,15 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, /* Second stage lookup */ im_address = pa; - ret = get_physical_address(env, &pa, &prot, im_address, + ret = get_physical_address(env, &pa, &prot2, im_address, access_type, mmu_idx, false, true); qemu_log_mask(CPU_LOG_MMU, "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx " prot %d\n", - __func__, im_address, ret, pa, prot); + __func__, im_address, ret, pa, prot2); + + prot &= prot2; if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret == TRANSLATE_SUCCESS) &&