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d="scan'208";a="136507031" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 30 Apr 2020 04:28:37 +0800 IronPort-SDR: czB2uXG5Am4w0utk6o1IiFdmUGHx/RFbram6MG4qE1zPZm6QIIDUZEms8gH4Hlqv7HqJXBqX7J 1ztGfUvOyn0hsRG1Dj9MhsIb8KNUkSOzA= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2020 13:18:42 -0700 IronPort-SDR: N0HD1fd4RSC5vwqzyKxKY1ZHL8P4JqS0eLuS6V5+yWnOowoFzHvROD4zMVA8CYHnYWdrYdC2Xv zn5i8EA30P+w== WDCIronportException: Internal Received: from usa004631.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.56.145]) by uls-op-cesaip01.wdc.com with ESMTP; 29 Apr 2020 13:28:37 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 01/14] riscv/sifive_u: Fix up file ordering Date: Wed, 29 Apr 2020 13:19:53 -0700 Message-Id: <20200429202006.775322-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429202006.775322-1-alistair.francis@wdc.com> References: <20200429202006.775322-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=381fbd49e=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/29 16:28:37 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , palmerdabbelt@google.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Split the file into clear machine and SoC sections. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/sifive_u.c | 108 ++++++++++++++++++++++---------------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 998666c91f..7f6a3c6c15 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -312,7 +312,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(nodename); } -static void riscv_sifive_u_init(MachineState *machine) +static void sifive_u_machine_init(MachineState *machine) { const struct MemmapEntry *memmap = sifive_u_memmap; SiFiveUState *s = RISCV_U_MACHINE(machine); @@ -403,6 +403,59 @@ static void riscv_sifive_u_init(MachineState *machine) &address_space_memory); } +static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) +{ + SiFiveUState *s = RISCV_U_MACHINE(obj); + + return s->start_in_flash; +} + +static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) +{ + SiFiveUState *s = RISCV_U_MACHINE(obj); + + s->start_in_flash = value; +} + +static void sifive_u_machine_instance_init(Object *obj) +{ + SiFiveUState *s = RISCV_U_MACHINE(obj); + + s->start_in_flash = false; + object_property_add_bool(obj, "start-in-flash", sifive_u_machine_get_start_in_flash, + sifive_u_machine_set_start_in_flash, NULL); + object_property_set_description(obj, "start-in-flash", + "Set on to tell QEMU's ROM to jump to " + "flash. Otherwise QEMU will jump to DRAM", + NULL); +} + +static void sifive_u_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "RISC-V Board compatible with SiFive U SDK"; + mc->init = sifive_u_machine_init; + mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; + mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; + mc->default_cpus = mc->min_cpus; +} + +static const TypeInfo sifive_u_machine_typeinfo = { + .name = MACHINE_TYPE_NAME("sifive_u"), + .parent = TYPE_MACHINE, + .class_init = sifive_u_machine_class_init, + .instance_init = sifive_u_machine_instance_init, + .instance_size = sizeof(SiFiveUState), +}; + +static void sifive_u_machine_init_register_types(void) +{ + type_register_static(&sifive_u_machine_typeinfo); +} + +type_init(sifive_u_machine_init_register_types) + static void riscv_sifive_u_soc_init(Object *obj) { MachineState *ms = MACHINE(qdev_get_machine()); @@ -443,33 +496,6 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_CADENCE_GEM); } -static bool sifive_u_get_start_in_flash(Object *obj, Error **errp) -{ - SiFiveUState *s = RISCV_U_MACHINE(obj); - - return s->start_in_flash; -} - -static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **errp) -{ - SiFiveUState *s = RISCV_U_MACHINE(obj); - - s->start_in_flash = value; -} - -static void riscv_sifive_u_machine_instance_init(Object *obj) -{ - SiFiveUState *s = RISCV_U_MACHINE(obj); - - s->start_in_flash = false; - object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_flash, - sifive_u_set_start_in_flash, NULL); - object_property_set_description(obj, "start-in-flash", - "Set on to tell QEMU's ROM to jump to " - "flash. Otherwise QEMU will jump to DRAM", - NULL); -} - static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) { MachineState *ms = MACHINE(qdev_get_machine()); @@ -607,29 +633,3 @@ static void riscv_sifive_u_soc_register_types(void) } type_init(riscv_sifive_u_soc_register_types) - -static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - - mc->desc = "RISC-V Board compatible with SiFive U SDK"; - mc->init = riscv_sifive_u_init; - mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; - mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; - mc->default_cpus = mc->min_cpus; -} - -static const TypeInfo riscv_sifive_u_machine_typeinfo = { - .name = MACHINE_TYPE_NAME("sifive_u"), - .parent = TYPE_MACHINE, - .class_init = riscv_sifive_u_machine_class_init, - .instance_init = riscv_sifive_u_machine_instance_init, - .instance_size = sizeof(SiFiveUState), -}; - -static void riscv_sifive_u_machine_init_register_types(void) -{ - type_register_static(&riscv_sifive_u_machine_typeinfo); -} - -type_init(riscv_sifive_u_machine_init_register_types)