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d="scan'208";a="136507044" Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 30 Apr 2020 04:28:41 +0800 IronPort-SDR: m2MDumlm9MQZc1JUC67mgeGikx6E5c5/ee83bGf6TtDCddpJ/NER3WCU8DyRFuHnXob/Erur5u Uzc0e93oLITWxheJ50vPBMEr1e29L6Ask= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2020 13:18:46 -0700 IronPort-SDR: pzY7k3hTMltQf7Kas/I5dpNyHuJPIJ3IyG7KJukIiQwS4cLLYPoAEGp5l/txjoLGxBnRNRLLC6 OXX55MqiCQyA== WDCIronportException: Internal Received: from usa004631.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.56.145]) by uls-op-cesaip01.wdc.com with ESMTP; 29 Apr 2020 13:28:41 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 14/14] hw/riscv/spike: Allow more than one CPUs Date: Wed, 29 Apr 2020 13:20:06 -0700 Message-Id: <20200429202006.775322-15-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429202006.775322-1-alistair.francis@wdc.com> References: <20200429202006.775322-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=381fbd49e=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/29 16:28:37 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Anup Patel , palmerdabbelt@google.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Anup Patel Currently, the upstream Spike ISA simulator allows more than one CPUs so we update QEMU Spike machine on similar lines to allow more than one CPUs. The maximum number of CPUs for QEMU Spike machine is kept same as QEMU Virt machine. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Message-id: 20200427080644.168461-4-anup.patel@wdc.com Message-Id: <20200427080644.168461-4-anup.patel@wdc.com> Signed-off-by: Alistair Francis --- hw/riscv/spike.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index e7908b88fe..d0c4843712 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -476,7 +476,7 @@ static void spike_machine_init(MachineClass *mc) { mc->desc = "RISC-V Spike Board"; mc->init = spike_board_init; - mc->max_cpus = 1; + mc->max_cpus = 8; mc->is_default = true; mc->default_cpu_type = SPIKE_V1_10_0_CPU; }