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d="scan'208";a="137935146" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 30 Apr 2020 02:37:06 +0800 IronPort-SDR: /zRL849gXteY/znLM78iVERjyJ5BR84DK/W9wRnq3LELcMgxIxfO8LtIPQv4JIlE0V/ZePf4kn adjDSV2vD9bqJ9NwkrWOCcTLEYXMk68ac= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2020 11:27:10 -0700 IronPort-SDR: 1dgaDGiAqqODlBTSFMFfNB6jSrEMkMF4WYn3AsXp+NkSV89OQFg9rGumJ1YBXM/8YaELiHUgFv ewwHpgjFyMuQ== WDCIronportException: Internal Received: from cnf007834.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.55.253]) by uls-op-cesaip01.wdc.com with ESMTP; 29 Apr 2020 11:37:04 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL 08/14] riscv: sifive_e: Support changing CPU type Date: Wed, 29 Apr 2020 11:28:50 -0700 Message-Id: <20200429182856.2588202-9-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429182856.2588202-1-alistair.francis@wdc.com> References: <20200429182856.2588202-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=381fbd49e=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/29 14:37:03 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Corey Wharton , palmerdabbelt@google.com, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Corey Wharton Allows the CPU to be changed from the default via the -cpu command line option. Signed-off-by: Corey Wharton Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200313193429.8035-2-coreyw7@fb.com Message-Id: <20200313193429.8035-2-coreyw7@fb.com> [ Changes by AF: - Set "cpu-type" from the machine and not SoC ] Signed-off-by: Alistair Francis --- hw/riscv/sifive_e.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 646553a7c3..b53109521e 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -123,8 +123,6 @@ static void riscv_sifive_e_soc_init(Object *obj) object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type", - &error_abort); object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", &error_abort); sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0", @@ -141,6 +139,8 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) SiFiveESoCState *s = RISCV_E_SOC(dev); MemoryRegion *sys_mem = get_system_memory(); + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type", + &error_abort); object_property_set_bool(OBJECT(&s->cpus), true, "realized", &error_abort); @@ -219,6 +219,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc) mc->desc = "RISC-V Board compatible with SiFive E SDK"; mc->init = riscv_sifive_e_init; mc->max_cpus = 1; + mc->default_cpu_type = SIFIVE_E_CPU; } DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)