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Tue, 28 Apr 2020 17:43:49 +0000 From: Stephen Long To: Subject: [PATCH RFC 3/3] target/arm: Implement SVE2 FCVTXNT Date: Tue, 28 Apr 2020 10:43:32 -0700 Message-ID: <20200428174332.17162-4-steplong@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200428174332.17162-1-steplong@quicinc.com> References: <20200428174332.17162-1-steplong@quicinc.com> X-ClientProxiedBy: MN2PR15CA0043.namprd15.prod.outlook.com (2603:10b6:208:237::12) To MWHPR0201MB3547.namprd02.prod.outlook.com (2603:10b6:301:7b::24) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from STEPLONG.qualcomm.com (108.176.222.2) by MN2PR15CA0043.namprd15.prod.outlook.com (2603:10b6:208:237::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2937.13 via Frontend Transport; Tue, 28 Apr 2020 17:43:48 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [108.176.222.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: efe098d0-a3e6-4148-2c05-08d7eb9bb52b X-MS-TrafficTypeDiagnostic: MWHPR0201MB3531: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:16; 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envelope-from=steplong@quicinc.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/28 13:43:52 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 199.106.114.38 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, richard.henderson@linaro.org, apazos@quicinc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Stephen Long --- target/arm/helper-sve.h | 2 ++ target/arm/sve.decode | 1 + target/arm/sve_helper.c | 7 +++++++ target/arm/translate-sve.c | 8 ++++++++ 4 files changed, 18 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 27a8cc2cbe..c18e4c01b0 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -2714,6 +2714,8 @@ DEF_HELPER_FLAGS_5(sve2_sqdmlsl_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve2_sqdmlsl_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_fcvtxnt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve2_fcvtnt_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve2_fcvtnt_ds, TCG_CALL_NO_RWG, diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 95fc7ee32c..cb4ed70698 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1480,6 +1480,7 @@ STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \ @rprr_scatter_store xs=0 esz=2 scale=0 ### SVE2 floating-point convert precision odd elements +FCVTXNT 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 FCVTLT_hs 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 8461d84445..56836d91cc 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -7591,6 +7591,13 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \ DO_FCVTNT(sve2_fcvtnt_sh, uint32_t, uint16_t, H1_4, H1_2, sve_f32_to_f16) DO_FCVTNT(sve2_fcvtnt_ds, uint64_t, uint32_t, H1_4, H1_2, float64_to_float32) +void HELPER(sve2_fcvtxnt)(void *vd, void *vn, void *vg, + void *status, uint32_t desc) +{ + set_float_rounding_mode(float_round_to_odd, status); + HELPER(sve2_fcvtnt_ds)(vd, vn, vg, status, desc); +} + #define DO_FCVTLT(NAME, TYPEW, TYPEN, HW, HN, OP) \ void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \ { \ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 220ff19348..b1cf24f6e7 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -8106,6 +8106,14 @@ static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_CMLA_zzzz *a) return do_sve2_zzzz_fn(s, a->rd, a->rn, a->rm, a->ra, fns[a->esz], a->rot); } +static bool trans_FCVTXNT(DisasContext *s, arg_rpr_esz *a) +{ + if (!dc_isar_feature(aa64_sve2, s)) { + return false; + } + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtxnt); +} + static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a) { if (!dc_isar_feature(aa64_sve2, s)) {