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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id x11sm126954ljj.15.2020.04.20.10.52.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 10:52:54 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PATCH v2 2/6] target/microblaze: Add the ill-opcode-exception property Date: Mon, 20 Apr 2020 19:52:46 +0200 Message-Id: <20200420175250.25777-3-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200420175250.25777-1-edgar.iglesias@gmail.com> References: <20200420175250.25777-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::244; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x244.google.com X-detected-operating-system: by eggs1p.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::244 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" Add the ill-opcode-exception property to control if illegal instructions will raise exceptions. Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Signed-off-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 4 ++++ target/microblaze/cpu.h | 1 + target/microblaze/translate.c | 2 +- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 1044120702..36c20d9724 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -207,6 +207,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) PVR2_DOPB_BUS_EXC_MASK : 0) | (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) | + (cpu->cfg.illegal_opcode_exception ? + PVR2_ILL_OPCODE_EXC_MASK : 0) | (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0); @@ -276,6 +278,8 @@ static Property mb_properties[] = { /* Enables bus exceptions on failed instruction fetches. */ DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU, cfg.iopb_bus_exception, false), + DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU, + cfg.illegal_opcode_exception, false), DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU, cfg.opcode_0_illegal, false), DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index d51587b342..71d7317a58 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -303,6 +303,7 @@ struct MicroBlazeCPU { bool endi; bool dopb_bus_exception; bool iopb_bus_exception; + bool illegal_opcode_exception; bool opcode_0_illegal; char *version; uint8_t pvr; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 222632b670..b4a78551ef 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -185,7 +185,7 @@ static void write_carryi(DisasContext *dc, bool carry) static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) - && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { + && dc->cpu->cfg.illegal_opcode_exception) { tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); }