From patchwork Tue Apr 14 20:06:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 185447 Delivered-To: patch@linaro.org Received: by 2002:a92:3d9a:0:0:0:0:0 with SMTP id k26csp1837762ilf; Tue, 14 Apr 2020 13:13:51 -0700 (PDT) X-Google-Smtp-Source: APiQypJNqZXH46i78SNl3BcfPs6tdu9/DmE+ZZKqMXnuItHVqKj/CjQdvgldb91RdrfRCoRRjX1o X-Received: by 2002:ac8:528d:: with SMTP id s13mr7908609qtn.160.1586895231228; Tue, 14 Apr 2020 13:13:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1586895231; cv=none; d=google.com; s=arc-20160816; b=LtY9fdWXZEUh8M+LgNH7V6IwT4wIRF7/EIb9piPmS0/51DMg427IDMjRc7luENvTAE YsdRzTjx4+vI7YBGpCEDdMB+z8UAHnN6uox8e2Ig1Aqv6ReLBiBCQJTLGWKwtL68vqZ/ GtqyH68hRM3MO05uVJ9WpBBNRhySrivqdQQlj8oaX15B+RvBS249brDdK6g/Maub51XP kT0n7A6dFPQNZA7SGKKrVDK/yAr+D58cr+z2Y6FiSaZ7hzaZj304Ff2RON8qn9aw9Ion DwHe3pPwEbtQhEY4x3xnUUNxqHC1tpuaGTAkjeGfY5CrNmHGwL0+v4PbA0/jU9umSzIN ArMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=en3XxeI0kUhj1g+8oDCU8qm2/eo411eCLElDQvibSv4=; b=xB6V3ABxp9YU0UYxtl8uOcAgDS3Er/bVqvGQrZsGlPV5grIZpJ66VyzHxnJajU/Hj+ xUCqjreIYmXvPWn1OVONPbSRYwu4f+kbsT/sQs2V1GASIoWlLz599ZOtROsqrkJvqvKn iPgAAGoFUrM8+53arFxKHU5gxCZT8f/s6W3bzfrNJ9EiZX3/nDjGR+xJvV1M4y2w15PA 6iAqHz/hKcbrVlahLpaDKwykDlMAhw8CGjc/z1+1haJqMTWf6rfIM6MzHljBz8Lx5W37 ZV1z1ctZNmeeFbNt+UWSU8xVvOHmaRS1nu1Lob3luwQGk5lhjf8c143K5saGloMxOyBY Wi9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=A7BCqQq3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n82si8673799qkn.80.2020.04.14.13.13.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 Apr 2020 13:13:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=A7BCqQq3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jORwM-0000MO-P8 for patch@linaro.org; Tue, 14 Apr 2020 16:13:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44492) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jORpU-000617-Kp for qemu-devel@nongnu.org; Tue, 14 Apr 2020 16:06:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jORpT-0005wW-6u for qemu-devel@nongnu.org; Tue, 14 Apr 2020 16:06:44 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:39755) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jORpT-0005wK-0U for qemu-devel@nongnu.org; Tue, 14 Apr 2020 16:06:43 -0400 Received: by mail-wm1-x341.google.com with SMTP id y24so15737876wma.4 for ; Tue, 14 Apr 2020 13:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=en3XxeI0kUhj1g+8oDCU8qm2/eo411eCLElDQvibSv4=; b=A7BCqQq3N+Wg72bkKjkAjNpf8sRBALo3rR1DHkl0MeO1HpWECTMdvIR4BgVqeLVY2M S9/ZFG2WHFHiaQ+rBEUzzd/H4jjOboS5wq/nAgDZSNXzeAziS/Cd/PMq+LQMd/mJVh9u vk1LBwC20ovfwekRoiMuYt85RGZ9tlsbo2x/zu/NbnMIvFy3Bb3GbFPw8O+oWuKfyjLY JpqAH2gv2efRDNNvdTa4C/dSyJ8auSM3qhFSdZC3qeXQLGs/WkIh4lJsrobSENQvB0uG ZQDuHxL5CJdCT5pSddpvx1I4UJlCUiWC1RHIfM9TKPvnaP03E2pW/AKIPfUy/FyVuyf0 Hxww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=en3XxeI0kUhj1g+8oDCU8qm2/eo411eCLElDQvibSv4=; b=WruGjUiYP/De4EYNKY+Z8CVLfm/r3dDmE6VMxMUyOXGIIy1L/f4pCMVI1dHRiVosEI Z2hWuXcKx2D2A+JOUaVZZRrrwFPO5AkUBQOZqCJTxMeZTvr/+tdbxIcNQKT+hzEb2D02 yM4k4idjqa8VPBTyDHaipv0cCsRU8awwVbyzlqtRnjSzhQ25Or54rd2Lpwyy8t6BToxT 35iVQD4vTseJ2mshUqFBMHsB8lYg0Ax2uhYHgyGEo6DaI0ruP616ikjFU5nkbnQFUZZh HDGlSSdmLG9ImCq3IJdJ5Z5gqQkM9gRmhmzn2yFRdNvSZlS0qeqyFft4pFEpKy5Tk9Ot FBzA== X-Gm-Message-State: AGi0PuZNWgRfNlr7Qg8Y1s2I4x8GDBs7GC2uhoqLLYwD2O0URkbs65Ew f+vgT0WMmwyqkf2rjtASylG+mA== X-Received: by 2002:a1c:e187:: with SMTP id y129mr1574429wmg.133.1586894802006; Tue, 14 Apr 2020 13:06:42 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id y9sm19405924wmm.26.2020.04.14.13.06.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Apr 2020 13:06:36 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 3AD241FF91; Tue, 14 Apr 2020 21:06:32 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v2 05/17] linux-user/ppc: Fix padding in mcontext_t for ppc64 Date: Tue, 14 Apr 2020 21:06:19 +0100 Message-Id: <20200414200631.12799-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200414200631.12799-1-alex.bennee@linaro.org> References: <20200414200631.12799-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Riku Voipio , Richard Henderson , Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The padding that was added in 95cda4c44ee was added to a union, and so it had no effect. This fixes misalignment errors detected by clang sanitizers for ppc64 and ppc64le. In addition, only ppc64 allocates space for VSX registers, so do not save them for ppc32. The kernel only has references to CONFIG_SPE in signal_32.c, so do not attempt to save them for ppc64. Fixes: 95cda4c44ee Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée --- linux-user/ppc/signal.c | 69 +++++++++++++++++------------------------ 1 file changed, 29 insertions(+), 40 deletions(-) -- 2.20.1 diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c index ecd99736b7e..20a02c197cb 100644 --- a/linux-user/ppc/signal.c +++ b/linux-user/ppc/signal.c @@ -35,12 +35,26 @@ struct target_mcontext { target_ulong mc_gregs[48]; /* Includes fpscr. */ uint64_t mc_fregs[33]; + #if defined(TARGET_PPC64) /* Pointer to the vector regs */ target_ulong v_regs; + /* + * On ppc64, this mcontext structure is naturally *unaligned*, + * or rather it is aligned on a 8 bytes boundary but not on + * a 16 byte boundary. This pad fixes it up. This is why we + * cannot use ppc_avr_t, which would force alignment. This is + * also why the vector regs are referenced in the ABI by the + * v_regs pointer above so any amount of padding can be added here. + */ + target_ulong pad; + /* VSCR and VRSAVE are saved separately. Also reserve space for VSX. */ + struct { + uint64_t altivec[34 + 16][2]; + } mc_vregs; #else target_ulong mc_pad[2]; -#endif + /* We need to handle Altivec and SPE at the same time, which no kernel needs to do. Fortunately, the kernel defines this bit to be Altivec-register-large all the time, rather than trying to @@ -48,32 +62,14 @@ struct target_mcontext { union { /* SPE vector registers. One extra for SPEFSCR. */ uint32_t spe[33]; - /* Altivec vector registers. The packing of VSCR and VRSAVE - varies depending on whether we're PPC64 or not: PPC64 splits - them apart; PPC32 stuffs them together. - We also need to account for the VSX registers on PPC64 - */ -#if defined(TARGET_PPC64) -#define QEMU_NVRREG (34 + 16) - /* On ppc64, this mcontext structure is naturally *unaligned*, - * or rather it is aligned on a 8 bytes boundary but not on - * a 16 bytes one. This pad fixes it up. This is also why the - * vector regs are referenced by the v_regs pointer above so - * any amount of padding can be added here - */ - target_ulong pad; -#else - /* On ppc32, we are already aligned to 16 bytes */ -#define QEMU_NVRREG 33 -#endif - /* We cannot use ppc_avr_t here as we do *not* want the implied - * 16-bytes alignment that would result from it. This would have - * the effect of making the whole struct target_mcontext aligned - * which breaks the layout of struct target_ucontext on ppc64. + /* + * Altivec vector registers. One extra for VRSAVE. + * On ppc32, we are already aligned to 16 bytes. We could + * use ppc_avr_t, but choose to share the same type as ppc64. */ - uint64_t altivec[QEMU_NVRREG][2]; -#undef QEMU_NVRREG + uint64_t altivec[33][2]; } mc_vregs; +#endif }; /* See arch/powerpc/include/asm/sigcontext.h. */ @@ -278,6 +274,7 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) __put_user((uint32_t)env->spr[SPR_VRSAVE], vrsave); } +#if defined(TARGET_PPC64) /* Save VSX second halves */ if (env->insns_flags2 & PPC2_VSX) { uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34]; @@ -286,6 +283,7 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) __put_user(*vsrl, &vsregs[i]); } } +#endif /* Save floating point registers. */ if (env->insns_flags & PPC_FLOAT) { @@ -296,22 +294,18 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame) __put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]); } +#if !defined(TARGET_PPC64) /* Save SPE registers. The kernel only saves the high half. */ if (env->insns_flags & PPC_SPE) { -#if defined(TARGET_PPC64) - for (i = 0; i < ARRAY_SIZE(env->gpr); i++) { - __put_user(env->gpr[i] >> 32, &frame->mc_vregs.spe[i]); - } -#else for (i = 0; i < ARRAY_SIZE(env->gprh); i++) { __put_user(env->gprh[i], &frame->mc_vregs.spe[i]); } -#endif /* Set MSR_SPE in the saved MSR value to indicate that frame->mc_vregs contains valid data. */ msr |= MSR_SPE; __put_user(env->spe_fscr, &frame->mc_vregs.spe[32]); } +#endif /* Store MSR. */ __put_user(msr, &frame->mc_gregs[TARGET_PT_MSR]); @@ -392,6 +386,7 @@ static void restore_user_regs(CPUPPCState *env, __get_user(env->spr[SPR_VRSAVE], vrsave); } +#if defined(TARGET_PPC64) /* Restore VSX second halves */ if (env->insns_flags2 & PPC2_VSX) { uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34]; @@ -400,6 +395,7 @@ static void restore_user_regs(CPUPPCState *env, __get_user(*vsrl, &vsregs[i]); } } +#endif /* Restore floating point registers. */ if (env->insns_flags & PPC_FLOAT) { @@ -412,22 +408,15 @@ static void restore_user_regs(CPUPPCState *env, env->fpscr = (uint32_t) fpscr; } +#if !defined(TARGET_PPC64) /* Save SPE registers. The kernel only saves the high half. */ if (env->insns_flags & PPC_SPE) { -#if defined(TARGET_PPC64) - for (i = 0; i < ARRAY_SIZE(env->gpr); i++) { - uint32_t hi; - - __get_user(hi, &frame->mc_vregs.spe[i]); - env->gpr[i] = ((uint64_t)hi << 32) | ((uint32_t) env->gpr[i]); - } -#else for (i = 0; i < ARRAY_SIZE(env->gprh); i++) { __get_user(env->gprh[i], &frame->mc_vregs.spe[i]); } -#endif __get_user(env->spe_fscr, &frame->mc_vregs.spe[32]); } +#endif } #if !defined(TARGET_PPC64)