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[209.51.188.17]) by mx.google.com with ESMTPS id r3si2732856qkd.153.2020.03.17.10.57.25 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 17 Mar 2020 10:57:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=g4vBGbR5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38202 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jEGSy-0002Ri-Kj for patch@linaro.org; Tue, 17 Mar 2020 13:57:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57320) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jEGN8-0000qp-2t for qemu-devel@nongnu.org; Tue, 17 Mar 2020 13:51:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jEGN5-0003kb-R3 for qemu-devel@nongnu.org; Tue, 17 Mar 2020 13:51:21 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:38705) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jEGN5-0003eQ-Hj for qemu-devel@nongnu.org; Tue, 17 Mar 2020 13:51:19 -0400 Received: by mail-wr1-x42a.google.com with SMTP id s1so5144015wrv.5 for ; Tue, 17 Mar 2020 10:51:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eaqvREUV5VO11iN7oPytlJwUMSXhsFBqTn8ICBLOQCM=; b=g4vBGbR5foez/fPhqL3znep8vnpvXRjT6ws79wzJgymHOI+MF18MasIPs5mYg0vLas e05VWFd3I0BFAxy4exIMfTR95kNB32gNCxQTdNm1EL347jBZF7exwc9WhCx6O/alPKPe qBmAzaK5pMRmBb+wilRdgjRLW/+RLOfkp0y/Ztu0oHinxMy88Cwmoy20oz3b0hsXuECs 5dXB2v0ekM23UF84dmZoEgpCYABuuEQnTvO9F9coJ91bTqx42U3yZgDsJdtPZodt803B q3La1a+jNwGq6xBTsVNHcqVmor2z0N2Fl7WcNmU5otSAAdRuTMDwaKcS9w0/bXmu86mD GGlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eaqvREUV5VO11iN7oPytlJwUMSXhsFBqTn8ICBLOQCM=; b=NitiDcSAh6ZigbDioTL1k/h+IPeIJORc4tUnG2kY1p7VjlVHRBULZR/idYR0Ujbmqv fMwP7i+LpyllM6P2BYy+PVbTviBNm/VZrqFXqfzXIyvoKQagb8ghbgfTJ9BW8gMIENKX mssPWy82TZUwSbaxGN8e+QciFMipTQ6HQ4V05AqDOCFZ+mrNOyvYge63zA8bAjInD4qK +Fw9THWeEjmtKisb/gnFFJq/NqdamsZfGbCE3Y1cI9w4m2LCqWEMnTZaNMWMJTTDjYW5 KqjGs2snyoG74lVycGe76xOcQIZoJzCSKwFdVe0PqZJDGz36OT1Po+ijONfeyKeTXDKX Jm7w== X-Gm-Message-State: ANhLgQ1QH0ILkDd6MxLXKLTm6maTkPPzTfgfNGWzsq+kuZGWyQIhPM1J zGbV1GsYrSaLwpDt9kYr2aIK3Q== X-Received: by 2002:adf:c44c:: with SMTP id a12mr198782wrg.172.1584467478348; Tue, 17 Mar 2020 10:51:18 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id 98sm5388291wrk.52.2020.03.17.10.51.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 10:51:12 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0B5F31FF9F; Tue, 17 Mar 2020 17:50:55 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Subject: [PULL 16/28] target/arm: explicitly encode regnum in our XML Date: Tue, 17 Mar 2020 17:50:41 +0000 Message-Id: <20200317175053.5278-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200317175053.5278-1-alex.bennee@linaro.org> References: <20200317175053.5278-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , "open list:ARM TCG CPUs" , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is described as optional but I'm not convinced of the numbering when multiple target fragments are sent. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20200316172155.971-17-alex.bennee@linaro.org> -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0ab82c987c3..fbfd73a7b5b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -980,7 +980,7 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); /* Dynamically generates for gdb stub an XML description of the sysregs from * the cp_regs hashtable. Returns the registered sysregs number. */ -int arm_gen_dynamic_sysreg_xml(CPUState *cpu); +int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg); /* Returns the dynamically generated XML for the gdb stub. * Returns a pointer to the XML contents for the specified XML file or NULL diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 1f68ab98c3b..69c35462a63 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -24,6 +24,7 @@ typedef struct RegisterSysregXmlParam { CPUState *cs; GString *s; + int n; } RegisterSysregXmlParam; /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect @@ -108,10 +109,11 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml, ARMCPRegInfo *ri, uint32_t ri_key, - int bitsize) + int bitsize, int regnum) { g_string_append_printf(s, "name); g_string_append_printf(s, " bitsize=\"%d\"", bitsize); + g_string_append_printf(s, " regnum=\"%d\"", regnum); g_string_append_printf(s, " group=\"cp_regs\"/>"); dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key; dyn_xml->num++; @@ -131,7 +133,8 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { if (arm_feature(env, ARM_FEATURE_AARCH64)) { if (ri->state == ARM_CP_STATE_AA64) { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64, + param->n++); } } else { if (ri->state == ARM_CP_STATE_AA32) { @@ -140,20 +143,22 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value, return; } if (ri->type & ARM_CP_64BIT) { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64, + param->n++); } else { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32); + arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32, + param->n++); } } } } } -int arm_gen_dynamic_sysreg_xml(CPUState *cs) +int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) { ARMCPU *cpu = ARM_CPU(cs); GString *s = g_string_new(NULL); - RegisterSysregXmlParam param = {cs, s}; + RegisterSysregXmlParam param = {cs, s, base_reg}; cpu->dyn_sysreg_xml.num = 0; cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs)); diff --git a/target/arm/helper.c b/target/arm/helper.c index b0e2a85b005..90135731353 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7973,7 +7973,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) 19, "arm-vfp.xml", 0); } gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_sysreg_xml(cs), + arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), "system-registers.xml", 0); }