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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 12/17] target/arm: Move the vfp decodetree calls next to the base isa Date: Mon, 24 Feb 2020 14:22:27 -0800 Message-Id: <20200224222232.13807-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Have the calls adjacent as an intermediate step toward actually merging the decodes. Signed-off-by: Richard Henderson --- v2: Fix fallthrough in disas_arm_insn vs vfp insns. --- target/arm/translate.c | 83 +++++++++++++++--------------------------- 1 file changed, 29 insertions(+), 54 deletions(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 5b7cad1ea2..6259064ea7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2646,31 +2646,6 @@ static void gen_neon_dup_high16(TCGv_i32 var) tcg_temp_free_i32(tmp); } -/* - * Disassemble a VFP instruction. Returns nonzero if an error occurred - * (ie. an undefined instruction). - */ -static int disas_vfp_insn(DisasContext *s, uint32_t insn) -{ - /* - * If the decodetree decoder handles this insn it will always - * emit code to either execute the insn or generate an appropriate - * exception; so we don't need to ever return non-zero to tell - * the calling code to emit an UNDEF exception. - */ - if (extract32(insn, 28, 4) == 0xf) { - if (disas_vfp_uncond(s, insn)) { - return 0; - } - } else { - if (disas_vfp(s, insn)) { - return 0; - } - } - /* If the decodetree decoder didn't handle this insn, it must be UNDEF */ - return 1; -} - static inline bool use_goto_tb(DisasContext *s, target_ulong dest) { #ifndef CONFIG_USER_ONLY @@ -10778,7 +10753,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) ARCH(5); /* Unconditional instructions. */ - if (disas_a32_uncond(s, insn)) { + /* TODO: Perhaps merge these into one decodetree output file. */ + if (disas_a32_uncond(s, insn) || + disas_vfp_uncond(s, insn)) { return; } /* fall back to legacy decoder */ @@ -10805,13 +10782,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } return; } - if ((insn & 0x0f000e10) == 0x0e000a00) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - return; - } if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10842,7 +10812,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) arm_skip_unless(s, cond); } - if (disas_a32(s, insn)) { + /* TODO: Perhaps merge these into one decodetree output file. */ + if (disas_a32(s, insn) || + disas_vfp(s, insn)) { return; } /* fall back to legacy decoder */ @@ -10852,11 +10824,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0xd: case 0xe: if (((insn >> 8) & 0xe) == 10) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - } else if (disas_coproc_insn(s, insn)) { + /* VFP, but failed disas_vfp. */ + goto illegal_op; + } + if (disas_coproc_insn(s, insn)) { /* Coprocessor. */ goto illegal_op; } @@ -10945,7 +10916,14 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) ARCH(6T2); } - if (disas_t32(s, insn)) { + /* + * TODO: Perhaps merge these into one decodetree output file. + * Note disas_vfp is written for a32 with cond field in the + * top nibble. The t32 encoding requires 0xe in the top nibble. + */ + if (disas_t32(s, insn) || + disas_vfp_uncond(s, insn) || + ((insn >> 28) == 0xe && disas_vfp(s, insn))) { return; } /* fall back to legacy decoder */ @@ -10962,17 +10940,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; /* op0 = 0b11 : unallocated */ } - if (disas_vfp_insn(s, insn)) { - if (((insn >> 8) & 0xe) == 10 && - dc_isar_feature(aa32_fpsp_v2, s)) { - /* FP, and the CPU supports it */ - goto illegal_op; - } else { - /* All other insns: NOCP */ - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), - default_exception_el(s)); - } + if (((insn >> 8) & 0xe) == 10 && + dc_isar_feature(aa32_fpsp_v2, s)) { + /* FP, and the CPU supports it */ + goto illegal_op; + } else { + /* All other insns: NOCP */ + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), + default_exception_el(s)); } break; } @@ -10995,9 +10971,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } } else if (((insn >> 8) & 0xe) == 10) { - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } + /* VFP, but failed disas_vfp. */ + goto illegal_op; } else { if (insn & (1 << 28)) goto illegal_op;