From patchwork Tue Feb 18 19:09:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183607 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp6465051ile; Tue, 18 Feb 2020 11:16:34 -0800 (PST) X-Google-Smtp-Source: APXvYqy94KVHVa8QAoZXhfMYLuwZWEc89bXmyABA1sr9yni1qnOdVXEbWvlWvGslqVp+H34WuE4u X-Received: by 2002:a37:4b4b:: with SMTP id y72mr19931856qka.175.1582053394613; Tue, 18 Feb 2020 11:16:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1582053394; cv=none; d=google.com; s=arc-20160816; b=CzvDcWnyhCK2cdUYi0QLVdstpwDZRNpFZOTMKcGH+NvvAXqolIp+dB0Z8VKeuOVF8v 3WZLLmlhaNOcam7anYrz4E3VEjdKfjdNcg8Kpf0IWR+6x1lrL9ysTLlSan/zAAi/n9QJ OhNvrGwmwFX/G9aj9lfi42Psx8tb8651L0ghkb0xVDFgejT9NOjm1nqB9ggBmG1dkld7 N6NiQsIjJ5tovcfidHQrIYSOqi9RMzCcW/izyDAssUIks/j/OJebpPOONVaUxtldfY2m WPeQkx0HrWcFwMoSVlZVMSya2kRj+7k3lkwcpOQyUKP1AOaMFuSlqz/9hTa3H/+OgIFB e7pA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aT+wiWpglSLXunTwVoN4RPF1V0ishR6Qd0crZF3h7bM=; b=ZrXdHxw5/ABL2Ye7vGpuQ2e/Ij2yZhVAto1dnqtX2eiSTvDtFYoD2VqHBnsfpaOZAX zCmu4Oij2J6qo+idG+kbHauU+bJWJh+R7HFhsUBUK/Vjfbd8fERjH3nLFLADyxbMsOJF 4x4KO+XDKAfKTX89k9tU2NeE0ukeDvhqBgOYgy96ZE2zNAjUjgMx5wZvs2WdszhSZRdP BGPYxtamlEHK83W73zbLMqSSu5ZJGLralLZyzraD2xF0isjCSNuiXvdNp1SIqId0Ojuk VsyJ1TgQAq40x8S1G17un0xAUHMxiH5r8yEIc+gcg+mCYLckc7nuMVLNFwX4MgwTBXIP USXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v8QubRib; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g13si2085926qtv.387.2020.02.18.11.16.34 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 18 Feb 2020 11:16:34 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v8QubRib; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40616 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j48ME-0006Dm-55 for patch@linaro.org; Tue, 18 Feb 2020 14:16:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46818) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j48Fz-0004wm-Ty for qemu-devel@nongnu.org; Tue, 18 Feb 2020 14:10:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j48Fy-0001qU-Fk for qemu-devel@nongnu.org; Tue, 18 Feb 2020 14:10:07 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:50639) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j48Fy-0001oS-9m for qemu-devel@nongnu.org; Tue, 18 Feb 2020 14:10:06 -0500 Received: by mail-pj1-x1041.google.com with SMTP id r67so1447057pjb.0 for ; Tue, 18 Feb 2020 11:10:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aT+wiWpglSLXunTwVoN4RPF1V0ishR6Qd0crZF3h7bM=; b=v8QubRibTLDCjL+qLjfh4h5/fAFDbGbXAy+5GhWoynru3nPS/7itzgaySkz1lo+GyN mTGRwKAbgDSCkvdEcncMXlvGPg4uyjmFTQmI6adYie4q3gPeTQnroRKNAKEFBUMZQpbV TPMawS9kxVptSWmGKWyD/n4io81KMAyehUuuOCxm6kGpgUeXN+1U0GSgIBCeixvvKYiS yisNbxm9QIqfN1KL0+WEPlLaII5qR1bGAirvYjmUllO5+rziLR+Ymuui0MwPbUZgluBp XrFejTmOqHnqQF0arcbtMI8a6LnHcL7Q1qkpIS5fCrPqfrJsvaHiRzR3uwHWkaj904r1 +Wow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aT+wiWpglSLXunTwVoN4RPF1V0ishR6Qd0crZF3h7bM=; b=k0VC4UzoqsFa2O+ZIWNjf3yywIj2fkJoqXb8oJND+tFjYujWXHWjqrzRyr1+f988S3 50at6s3tN9HfSTGlLHkjRtTjRPxXP7Utim1u4wWXJEjm8ypwg4PSW8ht6VhpCIoZu753 3tCgVrZi7FmP7E9nVAveL7Z9xhxkOCqnm+Zq3/nEmEinQi6WeE346oz+kFe1d1YDMKGh /O9rIEtZomu4AMZJLmu/GKzS9IPFYb3PPrH6+0/mg//Dpn8n4le28IfLHPBxWgULDfmz p+8AMsP8vNzqx/srwpyBErQGdSC+GERzrozD4UTKJy/slM6afjJhcAIuheAZfYNwscMS 1DFA== X-Gm-Message-State: APjAAAULjkJunFR8+rBJC0rSdJjfOQAdcQ2X9kgk3Y2uSmgvKOO2VObg da56EkhtNW11SZtHAr7VMP4poCfrLD0= X-Received: by 2002:a17:90a:fa8d:: with SMTP id cu13mr4328683pjb.68.1582053004856; Tue, 18 Feb 2020 11:10:04 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id i68sm5139399pfe.173.2020.02.18.11.10.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 11:10:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 3/7] target/arm: Honor the HCR_EL2.TSW bit Date: Tue, 18 Feb 2020 11:09:54 -0800 Message-Id: <20200218190958.745-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218190958.745-1-richard.henderson@linaro.org> References: <20200218190958.745-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These bits trap EL1 access to set/way cache maintenance insns. Buglink: https://bugs.launchpad.net/bugs/1863685 Signed-off-by: Richard Henderson --- target/arm/helper.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.c b/target/arm/helper.c index 8abbc4e991..dc99ee5d18 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -543,6 +543,16 @@ static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +/* Check for traps from EL1 due to HCR_EL2.TSW. */ +static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = env_archcpu(env); @@ -4704,14 +4714,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .access = PL1_W, .type = ARM_CP_NOP }, { .name = "DC_ISW", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, - .access = PL1_W, .type = ARM_CP_NOP }, + .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1, .access = PL0_W, .type = ARM_CP_NOP, .accessfn = aa64_cacheop_access }, { .name = "DC_CSW", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, - .access = PL1_W, .type = ARM_CP_NOP }, + .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1, .access = PL0_W, .type = ARM_CP_NOP, @@ -4722,7 +4732,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .accessfn = aa64_cacheop_access }, { .name = "DC_CISW", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, - .access = PL1_W, .type = ARM_CP_NOP }, + .access = PL1_W, .accessfn = access_tsw, .type = ARM_CP_NOP }, /* TLBI operations */ { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, @@ -4903,17 +4913,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, .type = ARM_CP_NOP, .access = PL1_W }, { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2, - .type = ARM_CP_NOP, .access = PL1_W }, + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1, .type = ARM_CP_NOP, .access = PL1_W }, { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2, - .type = ARM_CP_NOP, .access = PL1_W }, + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1, .type = ARM_CP_NOP, .access = PL1_W }, { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1, .type = ARM_CP_NOP, .access = PL1_W }, { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, - .type = ARM_CP_NOP, .access = PL1_W }, + .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw }, /* MMU Domain access control / MPU write buffer control */ { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, .resetvalue = 0,