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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i68sm5139399pfe.173.2020.02.18.11.10.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2020 11:10:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 1/7] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn Date: Tue, 18 Feb 2020 11:09:52 -0800 Message-Id: <20200218190958.745-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200218190958.745-1-richard.henderson@linaro.org> References: <20200218190958.745-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We had set this for aarch32-only in arm_max_initfn, but failed to set the same bit for aarch64. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) -- 2.20.1 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 32cf8ee98b..32c3e24a3d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -704,6 +704,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_mmfr3 = u; u = cpu->isar.id_mmfr4; + u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 implemented */ cpu->isar.id_mmfr4 = u;