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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id i3sm7525123pfg.94.2020.02.14.10.15.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 10:15:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/19] target/arm: Use isar_feature_aa32_simd_r32 more places Date: Fri, 14 Feb 2020 10:15:31 -0800 Message-Id: <20200214181547.21408-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org> References: <20200214181547.21408-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Many uses of ARM_FEATURE_VFP3 are testing for the number of simd registers implemented. Use the proper test vs MVCR0.SIMDReg. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 9 ++++----- target/arm/helper.c | 13 ++++++------- target/arm/translate.c | 2 +- 3 files changed, 11 insertions(+), 13 deletions(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.c b/target/arm/cpu.c index de733aceeb..f0bd419dd8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1009,11 +1009,10 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) if (flags & CPU_DUMP_FPU) { int numvfpregs = 0; - if (arm_feature(env, ARM_FEATURE_VFP)) { - numvfpregs += 16; - } - if (arm_feature(env, ARM_FEATURE_VFP3)) { - numvfpregs += 16; + if (cpu_isar_feature(aa32_simd_r32, cpu)) { + numvfpregs = 32; + } else if (arm_feature(env, ARM_FEATURE_VFP)) { + numvfpregs = 16; } for (i = 0; i < numvfpregs; i++) { uint64_t v = *aa32_vfp_dreg(env, i); diff --git a/target/arm/helper.c b/target/arm/helper.c index 366dbcf460..0eeedc3c18 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -49,10 +49,10 @@ static void switch_mode(CPUARMState *env, int mode); static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { - int nregs; + ARMCPU *cpu = env_archcpu(env); + int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; /* VFP data registers are always little-endian. */ - nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { stq_le_p(buf, *aa32_vfp_dreg(env, reg)); return 8; @@ -77,9 +77,9 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) { - int nregs; + ARMCPU *cpu = env_archcpu(env); + int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; - nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { *aa32_vfp_dreg(env, reg) = ldq_le_p(buf); return 8; @@ -905,8 +905,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, /* VFPv3 and upwards with NEON implement 32 double precision * registers (D0-D31). */ - if (!arm_feature(env, ARM_FEATURE_NEON) || - !arm_feature(env, ARM_FEATURE_VFP3)) { + if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ value |= (1 << 30); } @@ -7755,7 +7754,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) } else if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 51, "arm-neon.xml", 0); - } else if (arm_feature(env, ARM_FEATURE_VFP3)) { + } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 35, "arm-vfp3.xml", 0); } else if (arm_feature(env, ARM_FEATURE_VFP)) { diff --git a/target/arm/translate.c b/target/arm/translate.c index 20f89ace2f..3b9bf13933 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2612,7 +2612,7 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn) #define VFP_SREG(insn, bigbit, smallbit) \ ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1)) #define VFP_DREG(reg, insn, bigbit, smallbit) do { \ - if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \ + if (dc_isar_feature(aa32_simd_r32, s)) { \ reg = (((insn) >> (bigbit)) & 0x0f) \ | (((insn) >> ((smallbit) - 4)) & 0x10); \ } else { \