| Message ID | 20200214181547.21408-16-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: vfp feature and decodetree cleanup | expand |
On Fri, 14 Feb 2020 at 18:16, Richard Henderson <richard.henderson@linaro.org> wrote: > > Use isar feature tests instead of feature bit tests. > > Although none of QEMUs current cpus have VFPv3 without D32, > replace the large comment explaining why with one line that > sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions. > Mirror the test sequence used in the linux kernel. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > linux-user/elfload.c | 24 +++++++++++++++--------- > 1 file changed, 15 insertions(+), 9 deletions(-) > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index f3080a1635..c52c814a2e 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -468,22 +468,28 @@ static uint32_t get_elf_hwcap(void) > > /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */ > GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); > - GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); > GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); > GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); > GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); > - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); > GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); > - GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); > + GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); > + > GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA); > GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT); > - /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c. > - * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of > - * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated > - * to our VFP_FP16 feature bit. > + /* > + * Note that none of QEMU's cpus have double precision without single > + * precision support in VFP, so only test the single precision field. > */ Why not actually mirror the kernel's test sequence, rather than having a comment about how we deviate from it ? > - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPD32); > - GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); > + GET_FEATURE_ID(aa32_fpsp_v2, ARM_HWCAP_ARM_VFP); > + if (cpu_isar_feature(aa32_fpsp_v3, cpu)) { > + hwcaps |= ARM_HWCAP_ARM_VFPv3; > + if (cpu_isar_feature(aa32_simd_r32, cpu)) { > + hwcaps |= ARM_HWCAP_ARM_VFPD32; > + } else { > + hwcaps |= ARM_HWCAP_ARM_VFPv3D16; > + } > + } > + GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4); > > return hwcaps; > } thanks -- PMM
diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f3080a1635..c52c814a2e 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -468,22 +468,28 @@ static uint32_t get_elf_hwcap(void) /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */ GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); - GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); - GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); + GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); + GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA); GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT); - /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c. - * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of - * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated - * to our VFP_FP16 feature bit. + /* + * Note that none of QEMU's cpus have double precision without single + * precision support in VFP, so only test the single precision field. */ - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPD32); - GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); + GET_FEATURE_ID(aa32_fpsp_v2, ARM_HWCAP_ARM_VFP); + if (cpu_isar_feature(aa32_fpsp_v3, cpu)) { + hwcaps |= ARM_HWCAP_ARM_VFPv3; + if (cpu_isar_feature(aa32_simd_r32, cpu)) { + hwcaps |= ARM_HWCAP_ARM_VFPD32; + } else { + hwcaps |= ARM_HWCAP_ARM_VFPv3D16; + } + } + GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4); return hwcaps; }
Use isar feature tests instead of feature bit tests. Although none of QEMUs current cpus have VFPv3 without D32, replace the large comment explaining why with one line that sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions. Mirror the test sequence used in the linux kernel. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- linux-user/elfload.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) -- 2.20.1