| Message ID | 20200208125816.14954-7-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement PAN, ATS1E1, UAO | expand |
On Sat, 8 Feb 2020 at 12:58, Richard Henderson <richard.henderson@linaro.org> wrote: > > The J bit signals Jazelle mode, and so of course is RES0 > when the feature is not enabled. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > v4: Split out from aarch32_cpsr_valid_mask creation in previous patch. > --- > target/arm/internals.h | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/internals.h b/target/arm/internals.h index 4d4896fcdc..0569c96fd9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1064,7 +1064,7 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, const ARMISARegisters *id) { - uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV | CPSR_J; + uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; if ((features >> ARM_FEATURE_V4T) & 1) { valid |= CPSR_T; @@ -1078,6 +1078,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, if ((features >> ARM_FEATURE_THUMB2) & 1) { valid |= CPSR_IT; } + if (isar_feature_jazelle(id)) { + valid |= CPSR_J; + } return valid; }
The J bit signals Jazelle mode, and so of course is RES0 when the feature is not enabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v4: Split out from aarch32_cpsr_valid_mask creation in previous patch. --- target/arm/internals.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.20.1