From patchwork Sat Feb 8 12:58:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 183221 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp1947107ile; Sat, 8 Feb 2020 05:02:15 -0800 (PST) X-Google-Smtp-Source: APXvYqzw11hmjaeirkuG4cNHWzbAJxH6mdf3aNofx5h/4PqihggZcYLxy10CBKvzXcUGD+X4bq5V X-Received: by 2002:a05:620a:1333:: with SMTP id p19mr3313703qkj.73.1581166935009; Sat, 08 Feb 2020 05:02:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1581166935; cv=none; d=google.com; s=arc-20160816; b=hBN4YrlhziljBfVxZrbIohYMYgzdMScKI1YUY4jyfu5JIWfCBFa8a+4ECMr1zmgzdm VS84LEpj4KR5ak4skhRi/YwIMtmviyOpAhWNNg46zj6PtIL5/x3a8oxTXHne22zDyD5i 8wlpAAY24TZH+2YhCJgQjfNGlguCuGeJTXSTo2Q3b41ZN83JmH7NIh2SoqlNTt+KXtd2 tTPQKFmZNbGDKB/bneyOKZ4NDx882ejP+RBH1BHccR7hZ/IxxqX6TU3sXUAF9dPg6w6K uT82lixaTWyj5DjufVCDn/bAd9SQMnMDLYRd0Yzeq9a1Nw1ntqLIJAysexp1asBumgS3 CqIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=MWLtQ/ag+NbaBqsy4KxfJtC383rnR0ndbUAkAnWV62s=; b=SwkcRV2T0NIHThf21wPHo1Jk98D6cxk1q9gWDlV4HU5DpfCOFdYMECeNHwvHeOrlLx l3UbuZYFfAl8DfWLrH0iww3JBGwnLWenoil26XE1WZPto3exqXbSA3Bef+WDGS9FC3fC +D3JfX57gbf4SQSb1hcooWqHl8MIgL5BLla+QMl5T5LO2/mB3bHFEqGQMJQbxD4zLi2K OBak/0WHvtv6nyqnu4XiNR84RAaOYr5gVEvcZCs7uPSvToCPNiXo2KH/1yHCeKZKxYu3 31U9+eZPR67wmiXJ+haaDpAGy6eb+sJqcl8Kq0ZvUdKaotgiOv8dcvXaB19JTIeDwGyp zcUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q3x3wOZQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a188si1518156qke.248.2020.02.08.05.02.14 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:02:15 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q3x3wOZQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41024 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0PkT-0007XQ-DL for patch@linaro.org; Sat, 08 Feb 2020 08:02:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41377) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgn-0000PX-Bg for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgm-0004eM-7j for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:25 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:39683) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgm-0004cd-1X for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:24 -0500 Received: by mail-wr1-x444.google.com with SMTP id y11so2041590wrt.6 for ; Sat, 08 Feb 2020 04:58:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MWLtQ/ag+NbaBqsy4KxfJtC383rnR0ndbUAkAnWV62s=; b=q3x3wOZQvXuB4LPB4zbEIkoPpjRb6/jTBJMTTy1twEuLqqyWyH4TqLeFo0vNo+fu7m aIxA5obm0+l0DN/H7/iO/toOyWG+5rvNtgPzK1e7Yg0MClTJtIH6sWdlY6JUrdSv2eID ROxgrzlPunEemdY9ddnKyghpxTcrlb0l+XpA9BHlVKOTHdtgbCfUp+OFok+Q/sxFkqwT Bj3yN2JOa8uNsb4MRcg/OEOQEjBairL8BC+pTWOcdwOzBT9ykpJVQBI6Ym52merIimC8 BH2Sti/h9dJJi2OFf7gblPptrUbmtcq0DuXtKrNtC94bytgi1BLGmJM+EoHBVIj5edwx ywFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MWLtQ/ag+NbaBqsy4KxfJtC383rnR0ndbUAkAnWV62s=; b=bZ0rFw2OHzqONBnVu9i5p1iC0CweN9Dc8bvA9HWU6LBfBKDdoSJY5vd1l/rkfgmCfT +k/HdkKdE4qO//WvsDd4xRh9Y1JArs6tbI+c3QXvm2QMu8fuRRfUkvLchaNw5HFJvEqq PPQqKQuN7Suq/m4oXOCXWpW3a8KLtmq3MCobgnBuj7D4DFtcHVyoGwnF8OME3g2iaCby L7RvVIJTgFqIPzJmBIG2z4RjvwiqPGH9sz9+hjwjviWkocKsYci/FfGUXglY9zwpj/it dIQ1fUA4/6Ay1hyPtNTvyOIyIFokV0H4UTyKWwakoWUHfHGY46aixDSCP+rjh10XQw29 YUKw== X-Gm-Message-State: APjAAAXw5yIji6Crl41tnLvvfVDPHPGiswAX5JnfWyfx+jNzDPe5YnQE +xceApdsRO6zVh17ZrsvSXhVRdneR/SFLw== X-Received: by 2002:a5d:5273:: with SMTP id l19mr5608705wrc.175.1581166702843; Sat, 08 Feb 2020 04:58:22 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/20] target/arm: Split out aarch32_cpsr_valid_mask Date: Sat, 8 Feb 2020 12:58:01 +0000 Message-Id: <20200208125816.14954-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Split this helper out of msr_mask in translate.c. At the same time, transform the negative reductive logic to positive accumulative logic. It will be usable along the exception paths. While touching msr_mask, fix up formatting. Signed-off-by: Richard Henderson --- v4: Keep CPSR_J unconditionally in this patch. Fix all formatting in msr_mask. --- target/arm/internals.h | 21 +++++++++++++++++++++ target/arm/translate.c | 40 +++++++++++++++++----------------------- 2 files changed, 38 insertions(+), 23 deletions(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 6be8b2d1a9..4d4896fcdc 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1061,6 +1061,27 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) } } +static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, + const ARMISARegisters *id) +{ + uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV | CPSR_J; + + if ((features >> ARM_FEATURE_V4T) & 1) { + valid |= CPSR_T; + } + if ((features >> ARM_FEATURE_V5) & 1) { + valid |= CPSR_Q; /* V5TE in reality*/ + } + if ((features >> ARM_FEATURE_V6) & 1) { + valid |= CPSR_E | CPSR_GE; + } + if ((features >> ARM_FEATURE_THUMB2) & 1) { + valid |= CPSR_IT; + } + + return valid; +} + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. diff --git a/target/arm/translate.c b/target/arm/translate.c index d58c328e08..20f89ace2f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2734,39 +2734,33 @@ static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y) /* Return the mask of PSR bits set by a MSR instruction. */ static uint32_t msr_mask(DisasContext *s, int flags, int spsr) { - uint32_t mask; + uint32_t mask = 0; - mask = 0; - if (flags & (1 << 0)) + if (flags & (1 << 0)) { mask |= 0xff; - if (flags & (1 << 1)) + } + if (flags & (1 << 1)) { mask |= 0xff00; - if (flags & (1 << 2)) + } + if (flags & (1 << 2)) { mask |= 0xff0000; - if (flags & (1 << 3)) + } + if (flags & (1 << 3)) { mask |= 0xff000000; + } - /* Mask out undefined bits. */ - mask &= ~CPSR_RESERVED; - if (!arm_dc_feature(s, ARM_FEATURE_V4T)) { - mask &= ~CPSR_T; - } - if (!arm_dc_feature(s, ARM_FEATURE_V5)) { - mask &= ~CPSR_Q; /* V5TE in reality*/ - } - if (!arm_dc_feature(s, ARM_FEATURE_V6)) { - mask &= ~(CPSR_E | CPSR_GE); - } - if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) { - mask &= ~CPSR_IT; - } - /* Mask out execution state and reserved bits. */ + /* Mask out undefined and reserved bits. */ + mask &= aarch32_cpsr_valid_mask(s->features, s->isar); + + /* Mask out execution state. */ if (!spsr) { - mask &= ~(CPSR_EXEC | CPSR_RESERVED); + mask &= ~CPSR_EXEC; } + /* Mask out privileged bits. */ - if (IS_USER(s)) + if (IS_USER(s)) { mask &= CPSR_USER; + } return mask; }