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[209.51.188.17]) by mx.google.com with ESMTPS id g11si1469575qkm.233.2020.02.08.05.04.03 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 08 Feb 2020 05:04:03 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PNBFx+gu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41088 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0PmE-0002b5-Rl for patch@linaro.org; Sat, 08 Feb 2020 08:04:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41501) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j0Pgw-0000oV-Jr for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j0Pgv-0005BB-BV for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:34 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:40568) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j0Pgv-00058b-51 for qemu-devel@nongnu.org; Sat, 08 Feb 2020 07:58:33 -0500 Received: by mail-wr1-x442.google.com with SMTP id t3so2034453wru.7 for ; Sat, 08 Feb 2020 04:58:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5rep4zmfN+I/zzXm7mpLZvAoU6SaVw4L5kdUpJxxpog=; b=PNBFx+gu5l69Qc/iAOvWkB5jdyGzCHQT7O9KdZz7fU440YzNlOT3AzLJrpmwMpCquc iWw5LlOWhQf7Gp9sP6Y/UHBgto86e8+5EpVvUHZ4yGIdJaPIm/QLCWEuznZuXdxpE/nO YF2IkTedwtgv6nU7vgqSe1wglUJ0mY6gZiEhFZagLj7GzZ4TEoXP1rZiYWjbTZC2VdnQ +YFg2brZJMAANuBLVUpE6KHQ+1Groyz1lJ6dy51fqXIxKL1EtDt5W08LivwRDfxmt+T/ GtGmKU+C5Hvz9sCpYEnukb2sD5vD1sPJwzsE2ooeg3fMZhb/tsgTkMJtHrrBc/a+2TeM Y/hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5rep4zmfN+I/zzXm7mpLZvAoU6SaVw4L5kdUpJxxpog=; b=fAaM2N4J1ZpwZCnQhdl5nlkd3yUcEUG4ciIzU3+MTO21R5sg2iK4L2prPK0suRzP9b 4o4IcBWIjb+I3IoqZn+mTGfzrR8qKyBuTJPEKD7hJDIObtXhquMbcbisyKztO7viTSUL P4pTiNMP+L1NAq+7eLALdo1fQeYnTmSqMS3EFWAaKNHEfRTifFCrTfv1MOMIfyt0H34h 3cvqP741/p3K7i7I53Mb9A1QYirUCLriI0wTIjC0OTpRFZPyypRMbpAqWrjaJPNGmfIl LN7dbVj/0et8jowp2blwrYpbF0BjKNgkwJdRi3uO0+nHVsocTE5t9YitCNyjFU7u0Fxx EcnA== X-Gm-Message-State: APjAAAVX0Mc3F4le/LSScODVCF1rzyVr6rRbS3cseSGuBAiMAPzfSmJl zyUF/eeNXmT17LZ59gBtnsruHEK3EyxwoQ== X-Received: by 2002:adf:ecc6:: with SMTP id s6mr5451347wro.345.1581166711877; Sat, 08 Feb 2020 04:58:31 -0800 (PST) Received: from localhost.localdomain ([82.3.55.76]) by smtp.gmail.com with ESMTPSA id p5sm7490534wrt.79.2020.02.08.04.58.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Feb 2020 04:58:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/20] target/arm: Set PAN bit as required on exception entry Date: Sat, 8 Feb 2020 12:58:10 +0000 Message-Id: <20200208125816.14954-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200208125816.14954-1-richard.henderson@linaro.org> References: <20200208125816.14954-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The PAN bit is preserved, or set as per SCTLR_ELx.SPAN, plus several other conditions listed in the ARM ARM. Signed-off-by: Richard Henderson --- v2: Tidy preservation of CPSR_PAN in take_aarch32_exception (pmm). v4: Fix exception entry to EL3. --- target/arm/helper.c | 53 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 3 deletions(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.c b/target/arm/helper.c index 178757d271..de16ce79ad 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8763,8 +8763,12 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, uint32_t mask, uint32_t offset, uint32_t newpc) { + int new_el; + /* Change the CPU state so as to actually take the exception. */ switch_mode(env, new_mode); + new_el = arm_current_el(env); + /* * For exceptions taken to AArch32 we must clear the SS bit in both * PSTATE and in the old-state value we save to SPSR_, so zero it now. @@ -8777,7 +8781,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; /* Set new mode endianness */ env->uncached_cpsr &= ~CPSR_E; - if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { + if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { env->uncached_cpsr |= CPSR_E; } /* J and IL must always be cleared for exception entry */ @@ -8788,6 +8792,25 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; env->elr_el[2] = env->regs[15]; } else { + /* CPSR.PAN is normally preserved preserved unless... */ + if (cpu_isar_feature(aa64_pan, env_archcpu(env))) { + switch (new_el) { + case 3: + if (!arm_is_secure_below_el3(env)) { + /* ... the target is EL3, from non-secure state. */ + env->uncached_cpsr &= ~CPSR_PAN; + break; + } + /* ... the target is EL3, from secure state ... */ + /* fall through */ + case 1: + /* ... the target is EL1 and SCTLR.SPAN is 0. */ + if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { + env->uncached_cpsr |= CPSR_PAN; + } + break; + } + } /* * this is a lie, as there was no c1_sys on V4T/V5, but who cares * and we should just guard the thumb mode on V4 @@ -9050,6 +9073,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) unsigned int new_el = env->exception.target_el; target_ulong addr = env->cp15.vbar_el[new_el]; unsigned int new_mode = aarch64_pstate_mode(new_el, true); + unsigned int old_mode; unsigned int cur_el = arm_current_el(env); /* @@ -9129,20 +9153,43 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) } if (is_a64(env)) { - env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); + old_mode = pstate_read(env); aarch64_save_sp(env, arm_current_el(env)); env->elr_el[new_el] = env->pc; } else { - env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); + old_mode = cpsr_read(env); env->elr_el[new_el] = env->regs[15]; aarch64_sync_32_to_64(env); env->condexec_bits = 0; } + env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; + qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); + if (cpu_isar_feature(aa64_pan, cpu)) { + /* The value of PSTATE.PAN is normally preserved, except when ... */ + new_mode |= old_mode & PSTATE_PAN; + switch (new_el) { + case 2: + /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */ + if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) + != (HCR_E2H | HCR_TGE)) { + break; + } + /* fall through */ + case 1: + /* ... the target is EL1 ... */ + /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */ + if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) { + new_mode |= PSTATE_PAN; + } + break; + } + } + pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; aarch64_restore_sp(env, new_el);