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[120.151.179.201]) by smtp.gmail.com with ESMTPSA id b4sm5337844pfd.18.2020.01.08.18.49.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jan 2020 18:49:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/9] cputlb: Pass CPUTLBDescFast to tlb_n_entries and sizeof_tlb Date: Thu, 9 Jan 2020 13:49:01 +1100 Message-Id: <20200109024907.2730-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200109024907.2730-1-richard.henderson@linaro.org> References: <20200109024907.2730-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do not need the entire CPUArchState to compute these values. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) -- 2.20.1 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e4a8ed9534..49c605b6d8 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -80,14 +80,14 @@ QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_cpu_data)); QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1) -static inline size_t tlb_n_entries(CPUArchState *env, uintptr_t mmu_idx) +static inline size_t tlb_n_entries(CPUTLBDescFast *fast) { - return (env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS) + 1; + return (fast->mask >> CPU_TLB_ENTRY_BITS) + 1; } -static inline size_t sizeof_tlb(CPUArchState *env, uintptr_t mmu_idx) +static inline size_t sizeof_tlb(CPUTLBDescFast *fast) { - return env_tlb(env)->f[mmu_idx].mask + (1 << CPU_TLB_ENTRY_BITS); + return fast->mask + (1 << CPU_TLB_ENTRY_BITS); } static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, @@ -156,7 +156,7 @@ static void tlb_dyn_init(CPUArchState *env) static void tlb_mmu_resize_locked(CPUArchState *env, int mmu_idx) { CPUTLBDesc *desc = &env_tlb(env)->d[mmu_idx]; - size_t old_size = tlb_n_entries(env, mmu_idx); + size_t old_size = tlb_n_entries(&env_tlb(env)->f[mmu_idx]); size_t rate; size_t new_size = old_size; int64_t now = get_clock_realtime(); @@ -236,7 +236,8 @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx) env_tlb(env)->d[mmu_idx].large_page_addr = -1; env_tlb(env)->d[mmu_idx].large_page_mask = -1; env_tlb(env)->d[mmu_idx].vindex = 0; - memset(env_tlb(env)->f[mmu_idx].table, -1, sizeof_tlb(env, mmu_idx)); + memset(env_tlb(env)->f[mmu_idx].table, -1, + sizeof_tlb(&env_tlb(env)->f[mmu_idx])); memset(env_tlb(env)->d[mmu_idx].vtable, -1, sizeof(env_tlb(env)->d[0].vtable)); } @@ -622,7 +623,7 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; - unsigned int n = tlb_n_entries(env, mmu_idx); + unsigned int n = tlb_n_entries(&env_tlb(env)->f[mmu_idx]); for (i = 0; i < n; i++) { tlb_reset_dirty_range_locked(&env_tlb(env)->f[mmu_idx].table[i],