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[120.151.179.201]) by smtp.gmail.com with ESMTPSA id b4sm5337844pfd.18.2020.01.08.18.49.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jan 2020 18:49:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/9] cputlb: Make tlb_n_entries private to cputlb.c Date: Thu, 9 Jan 2020 13:49:00 +1100 Message-Id: <20200109024907.2730-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200109024907.2730-1-richard.henderson@linaro.org> References: <20200109024907.2730-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are no users of this function outside cputlb.c, and its interface will change in the next patch. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 5 ----- accel/tcg/cputlb.c | 5 +++++ 2 files changed, 5 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index a46116167c..53de19753a 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -234,11 +234,6 @@ static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, return (addr >> TARGET_PAGE_BITS) & size_mask; } -static inline size_t tlb_n_entries(CPUArchState *env, uintptr_t mmu_idx) -{ - return (env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS) + 1; -} - /* Find the TLB entry corresponding to the mmu_idx + address pair. */ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, target_ulong addr) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 1a81886e58..e4a8ed9534 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -80,6 +80,11 @@ QEMU_BUILD_BUG_ON(sizeof(target_ulong) > sizeof(run_on_cpu_data)); QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1) +static inline size_t tlb_n_entries(CPUArchState *env, uintptr_t mmu_idx) +{ + return (env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS) + 1; +} + static inline size_t sizeof_tlb(CPUArchState *env, uintptr_t mmu_idx) { return env_tlb(env)->f[mmu_idx].mask + (1 << CPU_TLB_ENTRY_BITS);