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[209.51.188.17]) by mx.google.com with ESMTPS id 83si5362514qkj.334.2019.12.20.04.22.32 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Dec 2019 04:22:32 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=H7fqNRwd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiHIe-0002qt-5N for patch@linaro.org; Fri, 20 Dec 2019 07:22:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36283) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iiHAr-0000dv-VU for qemu-devel@nongnu.org; Fri, 20 Dec 2019 07:14:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iiHAq-0001FF-9b for qemu-devel@nongnu.org; Fri, 20 Dec 2019 07:14:29 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:46382) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iiHAp-00019u-Uj for qemu-devel@nongnu.org; Fri, 20 Dec 2019 07:14:28 -0500 Received: by mail-wr1-x443.google.com with SMTP id z7so9163500wrl.13 for ; Fri, 20 Dec 2019 04:14:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KRu49EbgGVQ7V2rxhXNHs855imxrN5MTwZSo9giC7oo=; b=H7fqNRwdjB5hRPbOqjSzn3+92GkPWo2OL6At9HiFJ849JvF6TXaExMH38Jhn65KSh1 qoPED6b3NLZASeBJKKMcPoWXptmNZglhfPOaQxVR6gLA6Ao5So503ISzRoJZxqKm4PVX X1Qgk/bP5I2fSIFfCxTWiKGLvuYlkan7LYKxQDYCVj+hibAwZ6oThn5C9j5xoh9Wjvl0 3Y60fPxB28nL2F0HMdn1xQgKBOy1ofEXAuapr+thnXdzyMidic8Y125WGysvN1pAD57m PGNArncAjLnLlNYOD2qlV7DZcPbfZHvlNNQGfjXfAqHmBS/35mG2COdGwcLe3XzjFhP9 D1qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KRu49EbgGVQ7V2rxhXNHs855imxrN5MTwZSo9giC7oo=; b=J74Qu25/7jnSjsjQK0SLThR53zaEekvqv1Q6NjXmgMt+3sLVjeM/622eWWQ2ZrZgUv QIvK/17m9qoLLnqeSrugxU24Ot1xPGHSdBy06HuHEgg/GRrhxhEdzADprYP7v+tprFGE O2kpBXubVHVjjEAimpd9JZ/2VJXDebmxzH5zanNDwIMhcJDl4RdMh1SYHPa66juhfwld s19iJzypHqgwRuaz7AL7X0k6xA4cOOgTUDfHLcgXKIeDsHTJAEv6npwHEPtXNxI8KQ4b SgAx5AWUnzMxgPyEkVUD8XJwgs4qiJ53jNSsme2g/tE8bAaLyYxFFZBT6hlosIRt2tJH mbbA== X-Gm-Message-State: APjAAAVlDOGmmH/Mh03qwFpmq7Haj7SHgeVzzOnYkPU0LOV1ZZetbYpZ RmI0DoThcwu2/iDLk0weY6Mwsg== X-Received: by 2002:adf:93c5:: with SMTP id 63mr15130458wrp.236.1576844066353; Fri, 20 Dec 2019 04:14:26 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id f207sm10901781wme.9.2019.12.20.04.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Dec 2019 04:14:25 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6CBB11FF9E; Fri, 20 Dec 2019 12:04:40 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v4 14/21] target/arm: don't bother with id_aa64pfr0_read for USER_ONLY Date: Fri, 20 Dec 2019 12:04:31 +0000 Message-Id: <20191220120438.16114-15-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191220120438.16114-1-alex.bennee@linaro.org> References: <20191220120438.16114-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: damien.hedde@greensocs.com, Peter Maydell , luis.machado@linaro.org, Richard Henderson , "open list:ARM TCG CPUs" , alan.hayward@arm.com, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For system emulation we need to check the state of the GIC before we report the value. However this isn't relevant to exporting of the value to linux-user and indeed breaks the exported value as set by modify_arm_cp_regs. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - extend the ifdef and make type CONST with no accessfn --- target/arm/helper.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 857581feba4..23de21f8820 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5912,6 +5912,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) return pfr1; } +#ifndef CONFIG_USER_ONLY static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = env_archcpu(env); @@ -5922,6 +5923,7 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) } return pfr0; } +#endif /* Shared logic between LORID and the rest of the LOR* registers. * Secure state has already been delt with. @@ -6414,16 +6416,24 @@ void register_cp_regs_for_features(ARMCPU *cpu) * define new registers here. */ ARMCPRegInfo v8_idregs[] = { - /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't - * know the right value for the GIC field until after we - * define these regs. + /* + * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system + * emulation because we don't know the right value for the + * GIC field until after we define these regs. */ { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, - .access = PL1_R, .type = ARM_CP_NO_RAW, + .access = PL1_R, +#ifdef CONFIG_USER_ONLY + .type = ARM_CP_CONST, + .resetvalue = cpu->isar.id_aa64pfr0 +#else + .type = ARM_CP_NO_RAW, .accessfn = access_aa64_tid3, .readfn = id_aa64pfr0_read, - .writefn = arm_cp_write_ignore }, + .writefn = arm_cp_write_ignore +#endif + }, { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,