From patchwork Tue Dec 3 22:53:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 180777 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp2196030ile; Tue, 3 Dec 2019 15:29:09 -0800 (PST) X-Google-Smtp-Source: APXvYqzNiq6qpXxqyaNdJrwFm397qIYrZMCHmEqno9ZI32UcydBxqPLakSSf/LbRK+KX6fBRnEx6 X-Received: by 2002:a37:9d51:: with SMTP id g78mr32606qke.142.1575415749259; Tue, 03 Dec 2019 15:29:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575415749; cv=none; d=google.com; s=arc-20160816; b=v6r+6p6T1o4hej2655exC9QbhgQehGh3vWCteofmHgDaaXxlL8MPriW5wOtESLD3h3 fW+wHJSnsN3D+qLypgldgc2e4NtX1FKg6PyA/AzzI25kJ83jqpAQnGiUuv918ZOd3xAN RRFJRCGTzK2IqF4r+TDsYJbxNOaTmkBD6NAxs7W9QheMXYGnZC7ouQ8JiDMNSAjovYTi 57HI/q7WRiG0y9AQ9RA2LYtGe2OksiP7rc/X0kDEA2zjvplJb3eIv90qz/lKZVdE0ckG k7uKHlOBplZTpNZvQHGeUPu1SuP4ASHKlDG6PL8eKjTxIfdYPUNXHioHUZkSx0xCthZ/ gU7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=yh3Zl0Yfgd5t5mYjFXJ95PB0dxs1Lxcsdr6CBQV1gYs=; b=ZL7xMjOe0DtbaRtTKwQW78C4qVhVcSFVQTvjx25ooq+9MbUItlSURNlqBwF7DOMfLS mLanVUByjowAsXNpS6d2sS2zdYK3TuIrU8aVJvJeYJrWovdr1AdYeR61Rlzrf6zTzK1g 4qgNG84i0SJNyX3ZtGKQOD7X6lrm+9Qeqr1X/M+qsh4NjP7vk/K+vDeqeJna+5qtnqPR 0LtmvxHELR3onWq0AmtPUtef3TXvb6i8ozgJpEIW/HSpSMcFFpfRLiY57ALmJrcuqdqw PCJqTqIW9IjqIjYa/i4UxPGsE3nJI2DX0x5Vh3SnNtAVtgaVAaU6wN9rWre+GmZU8H40 ci4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MO5NaQ+f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q203si3452791qke.268.2019.12.03.15.29.09 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Dec 2019 15:29:09 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MO5NaQ+f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icHbQ-0006m1-R4 for patch@linaro.org; Tue, 03 Dec 2019 18:29:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58628) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1icH3e-0002wo-U1 for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1icH3Z-0006vN-AG for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:11 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:35018) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1icH3V-0006bt-UA for qemu-devel@nongnu.org; Tue, 03 Dec 2019 17:54:07 -0500 Received: by mail-pj1-x1041.google.com with SMTP id w23so1032520pjd.2 for ; Tue, 03 Dec 2019 14:53:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yh3Zl0Yfgd5t5mYjFXJ95PB0dxs1Lxcsdr6CBQV1gYs=; b=MO5NaQ+fWAcCRw8VDgNrpdsX+WE2S6qwB+PHclgbzfqvmArsAARrtN2c3SHs25Vkmv Cro5Zf6oeiRfhtmRbH6sFrgJGbmu1uSiQ3uVLtMAdVNqVM8aFciYg9CJK0p0vwPMtU07 CGPsy8tp7a3O4pSeIGPk98/FPFdn75Bi/nXOZcizAcP8Gbsv2Ood4iIf/YsmVjM7Z2qa 0tPgcakSmNCO/kbPqE9QfzFc6d8ya7sGR7QB2u29z7gxOktq/atKaG/rM1UYY87aQkhQ Oy5CfGzCUPFeOoWho3HAx3V8JKLDM2vE4Tax0vNiLfbZEOOApSh6u68LfirTR7U5Nvos MYAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yh3Zl0Yfgd5t5mYjFXJ95PB0dxs1Lxcsdr6CBQV1gYs=; b=k61auEUPGg2RJV6KGzMvcQYoUB/v5Ut6efjVgEQiQ0VgGNzI8YuT8Et2lugyPTUPDo qtnum2skrkmjCErB7BJygjxvunKJMV3NxGdSJHfyMNtGTfDl9pt7kmN0ICehQsOcSOA+ DaUSct20ZeLCDIVe106yrNvlTheIAfrEO0Rl1hzApemyLAl4j/zW+l+F2sluWvnLJtbF VQCvYJ65NUIFdV5oC3UkgEEf17ykb1fhs5ODw5/9zJgZzxzqqoY1/qpvqafMNTiMYPXJ C5kxSqmwtfJoxTWulDmxcmEyo1P1mwFH7rao+JO3AdWWyk2mwWfjVceafK7tKCNlyTQx HJxw== X-Gm-Message-State: APjAAAXbsmu/w6M7p3VZ+3rh2ueFhFcSLyb83XI+H8umK6Z0r/xZ440i po8diXefmwp2x5zmCLDGrDibOIiZNWE= X-Received: by 2002:a17:902:d201:: with SMTP id t1mr367250ply.322.1575413628230; Tue, 03 Dec 2019 14:53:48 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d22sm3789713pjd.2.2019.12.03.14.53.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2019 14:53:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/11] target/arm: Implement ATS1E1 system registers Date: Tue, 3 Dec 2019 14:53:32 -0800 Message-Id: <20191203225333.17055-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203225333.17055-1-richard.henderson@linaro.org> References: <20191203225333.17055-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a minor enhancement over ARMv8.1-PAN. The *_PAN mmu_idx are used with the existing do_ats_write. Signed-off-by: Richard Henderson --- target/arm/helper.c | 50 +++++++++++++++++++++++++++++++++++++++------ 1 file changed, 44 insertions(+), 6 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.c b/target/arm/helper.c index 043e44d73d..f1eab4fb28 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3360,16 +3360,20 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) switch (ri->opc2 & 6) { case 0: - /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ + /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */ switch (el) { case 3: mmu_idx = ARMMMUIdx_SE3; break; case 2: - mmu_idx = ARMMMUIdx_Stage1_E1; - break; + g_assert(!secure); /* TODO: ARMv8.4-SecEL2 */ + /* fall through */ case 1: - mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; + if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { + mmu_idx = secure ? ARMMMUIdx_SE1_PAN : ARMMMUIdx_Stage1_E1_PAN; + } else { + mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; + } break; default: g_assert_not_reached(); @@ -3438,8 +3442,12 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, switch (ri->opc2 & 6) { case 0: switch (ri->opc1) { - case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; + case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ + if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { + mmu_idx = secure ? ARMMMUIdx_SE1_PAN : ARMMMUIdx_Stage1_E1_PAN; + } else { + mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; + } break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx = ARMMMUIdx_E2; @@ -7426,6 +7434,36 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_arm_cp_regs(cpu, pan_reginfo); } +#ifndef CONFIG_USER_ONLY + if (cpu_isar_feature(aa64_ats1e1, cpu)) { + static const ARMCPRegInfo ats1e1_reginfo[] = { + { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, + { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, ats1e1_reginfo); + } + if (cpu_isar_feature(aa32_ats1e1, cpu)) { + static const ARMCPRegInfo ats1cp_reginfo[] = { + { .name = "ATS1CPRP", + .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write }, + { .name = "ATS1CPWP", + .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, ats1cp_reginfo); + } +#endif if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { static const ARMCPRegInfo vhe_reginfo[] = {