diff mbox series

[v4,22/40] target/arm: Update aa64_zva_access for EL2

Message ID 20191203022937.1474-23-richard.henderson@linaro.org
State Superseded
Headers show
Series target/arm: Implement ARMv8.1-VHE | expand

Commit Message

Richard Henderson Dec. 3, 2019, 2:29 a.m. UTC 
The comment that we don't support EL2 is somewhat out of date.
Update to include checks against HCR_EL2.TDZ.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/helper.c | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

-- 
2.17.1

Comments

Alex Bennée Dec. 4, 2019, 3:01 p.m. UTC | #1 
Richard Henderson <richard.henderson@linaro.org> writes:

> The comment that we don't support EL2 is somewhat out of date.

> Update to include checks against HCR_EL2.TDZ.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


> ---

>  target/arm/helper.c | 26 +++++++++++++++++++++-----

>  1 file changed, 21 insertions(+), 5 deletions(-)

>

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index 4f5e0b656c..ffa82b5509 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -4109,11 +4109,27 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,

>  static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,

>                                        bool isread)

>  {

> -    /* We don't implement EL2, so the only control on DC ZVA is the

> -     * bit in the SCTLR which can prohibit access for EL0.

> -     */

> -    if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {

> -        return CP_ACCESS_TRAP;

> +    int cur_el = arm_current_el(env);

> +

> +    if (cur_el < 2) {

> +        uint64_t hcr = arm_hcr_el2_eff(env);

> +

> +        if (cur_el == 0) {

> +            if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {

> +                if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) {

> +                    return CP_ACCESS_TRAP_EL2;

> +                }

> +            } else {

> +                if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) {

> +                    return CP_ACCESS_TRAP;

> +                }

> +                if (hcr & HCR_TDZ) {

> +                    return CP_ACCESS_TRAP_EL2;

> +                }

> +            }

> +        } else if (hcr & HCR_TDZ) {

> +            return CP_ACCESS_TRAP_EL2;

> +        }

>      }

>      return CP_ACCESS_OK;

>  }



-- 
Alex Bennée
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 4f5e0b656c..ffa82b5509 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4109,11 +4109,27 @@  static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                       bool isread)
 {
-    /* We don't implement EL2, so the only control on DC ZVA is the
-     * bit in the SCTLR which can prohibit access for EL0.
-     */
-    if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
-        return CP_ACCESS_TRAP;
+    int cur_el = arm_current_el(env);
+
+    if (cur_el < 2) {
+        uint64_t hcr = arm_hcr_el2_eff(env);
+
+        if (cur_el == 0) {
+            if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
+                if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) {
+                    return CP_ACCESS_TRAP_EL2;
+                }
+            } else {
+                if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
+                    return CP_ACCESS_TRAP;
+                }
+                if (hcr & HCR_TDZ) {
+                    return CP_ACCESS_TRAP_EL2;
+                }
+            }
+        } else if (hcr & HCR_TDZ) {
+            return CP_ACCESS_TRAP_EL2;
+        }
     }
     return CP_ACCESS_OK;
 }