From patchwork Tue Dec 3 02:29:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 180663 Delivered-To: patch@linaro.org Received: by 2002:a92:3001:0:0:0:0:0 with SMTP id x1csp940082ile; Mon, 2 Dec 2019 18:37:31 -0800 (PST) X-Google-Smtp-Source: APXvYqxJXG2vYvDsvweNCdAmIJGyCabsH0ZIhjnXiS0VTbAIJTGKxvH5vYtP++K8zk5cHA5XMMLY X-Received: by 2002:aed:2a39:: with SMTP id c54mr3085380qtd.339.1575340651740; Mon, 02 Dec 2019 18:37:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575340651; cv=none; d=google.com; s=arc-20160816; b=pEy8K7BSFeckZVTm0Fj9XBsC5ibzCgNFXLRiTlAmlqETxL+0SOxN7XP7K/HhbkKZU6 vOCED5XbLgWeYN857ZMQHZ42eJuedJ/KjNpYoJgWdF0N3zPSiwqyQ/f60acyN++pUekL wMWPGwNc9LVzMUWAD92dnOhOP7bD+HuvAy9t9f1UqhMEfGVPHW8zoeBo6HbMjoX2d+zX auTuNqHXKN81s39BbShI9FL+lATr+MvTUM44uE9Ae3NfWBpuNci9YArnEDfNM5SWUHiS qu52GC5A1EpxJPqnwAhAKChslbtO4HVgp26XUWiM6vzzfV9QJ7ttRpBFt987371NB5e0 8URQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=WeZRzsGyAYlGhck3WxuFXMlnAxw7pFnicVDnjAR9k4Q=; b=PuQYvdEEeg1ctyb0TpoCTHwwacCf9OuqDwe3wsAs8/MPm3OaZ57yFhMGzMK2ZkE37c LBhI9841pbJm/EwMVhEziehu8Ff7KVwlQZaNMJUpl+Cr/43YDCkd1wQR5/olpi5+bkoC 14M9njKktynzOl6/p82hn1O+3ea9MEdfA0mYA7dcUfYciu6X6PZDfLRyLzczWWRxPEGa QKm/J3zsotiF/SnldTEuP2BNDOTywFt4XOk9+s3Y7zRbtkC63MmbCtVDUfiZQBZTGOp6 QMeIxUHkd+qM7RRBkIZXOkpCY5HDkjVdGZOBdapu31qnJSWA/Fgb6hzM6tgsAigDNPTd UDZg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=x7+sWNn1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w2si1083595qvt.11.2019.12.02.18.37.31 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Dec 2019 18:37:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=x7+sWNn1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47228 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iby4B-0002Rn-2u for patch@linaro.org; Mon, 02 Dec 2019 21:37:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60022) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ibxwt-0003Bt-2Y for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:30:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ibxwq-0008A3-US for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:58 -0500 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:45213) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ibxwq-00087a-Dh for qemu-devel@nongnu.org; Mon, 02 Dec 2019 21:29:56 -0500 Received: by mail-pf1-x443.google.com with SMTP id 2so963437pfg.12 for ; Mon, 02 Dec 2019 18:29:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WeZRzsGyAYlGhck3WxuFXMlnAxw7pFnicVDnjAR9k4Q=; b=x7+sWNn1LjIC60mkzA5oK58DcLGLIyuMKyGN7/eGd0n30X1CncrOw3Grhqdn08qX7X 9PRE2IBm1dHI3wB9kttp5KsF1DCjwdEleSHPqb7xuZFzi2u4BDKTpjZKcmA7hR5Jxg48 TCKpHP7VJg8iwjShYsxE4R9Liews5WQWKWyubqKs0u8R1A04SzTfYxZAdbCb95hh+C3w fib96yXtioiaPF5yd5/nbCD9HmLaw43IPysuK1T5FUwuN3SuuZpgbg3BC34o1Lw21Ph7 64M/Q2L/EKrB5LrKdgdfGxAm3k62aRiSEHuXPrstSczlo47SCDxJhnkmnUxZR1mzI2lE H4wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WeZRzsGyAYlGhck3WxuFXMlnAxw7pFnicVDnjAR9k4Q=; b=Qm5OOtPx50hBKNSTZoofzwwggyBEvHh/q0i7eJzUsNgakIfQEkvKj5EwepylbwSfn7 vL4STuJ7fiJlMTZHDBi3e8WFt+wwEDbTYFYNIR/C7hgkynmbn0/yQyV5XMtSu7kdEMCI A4VGMwYtPPOpPDmxwwYyrH1cMThFjCAP1EXDVSXKXtULmprSpet2dMd0Cup8k+Jw1VJL oq6q+XLe8mls+qk+g0XYxI5CNjboZCqGpDa5Si9AcMU73Q3bBt3NafofhJuv4bvHCgct 4WkMbloQ/hq/p+jTtue4ZfAjyko/Cnmnny1Fh1mRapbENX3QoQCysFfRPZjIm+Gnn8DZ pHZg== X-Gm-Message-State: APjAAAXZhPKO/dGH1LM9H7Nct5hmuGG7DQWUbe/fncgHGzVszO32s5zq M8RwAECrv8TdhMANLF9lJWnfwvxFSkI= X-Received: by 2002:a63:d551:: with SMTP id v17mr2867349pgi.365.1575340193900; Mon, 02 Dec 2019 18:29:53 -0800 (PST) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id q22sm873695pfg.170.2019.12.02.18.29.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 18:29:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/40] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE* Date: Mon, 2 Dec 2019 18:29:08 -0800 Message-Id: <20191203022937.1474-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191203022937.1474-1-richard.henderson@linaro.org> References: <20191203022937.1474-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is part of a reorganization to the set of mmu_idx. The Secure regimes all have a single stage translation; there is no point in pointing out that the idx is for stage1. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 ++++---- target/arm/internals.h | 4 ++-- target/arm/translate.h | 2 +- target/arm/helper.c | 26 +++++++++++++------------- target/arm/translate-a64.c | 4 ++-- target/arm/translate.c | 6 +++--- 6 files changed, 25 insertions(+), 25 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0714c52176..e8ee316e05 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2868,8 +2868,8 @@ typedef enum ARMMMUIdx { ARMMMUIdx_EL10_1 = 1 | ARM_MMU_IDX_A, ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A, ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A, - ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A, + ARMMMUIdx_SE0 = 4 | ARM_MMU_IDX_A, + ARMMMUIdx_SE1 = 5 | ARM_MMU_IDX_A, ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A, ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M, @@ -2894,8 +2894,8 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_EL10_1 = 1 << 1, ARMMMUIdxBit_S1E2 = 1 << 2, ARMMMUIdxBit_S1E3 = 1 << 3, - ARMMMUIdxBit_S1SE0 = 1 << 4, - ARMMMUIdxBit_S1SE1 = 1 << 5, + ARMMMUIdxBit_SE0 = 1 << 4, + ARMMMUIdxBit_SE1 = 1 << 5, ARMMMUIdxBit_Stage2 = 1 << 6, ARMMMUIdxBit_MUser = 1 << 0, ARMMMUIdxBit_MPriv = 1 << 1, diff --git a/target/arm/internals.h b/target/arm/internals.h index 3fd1518f3b..3600bf9122 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -820,8 +820,8 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_MUser: return false; case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: + case ARMMMUIdx_SE0: + case ARMMMUIdx_SE1: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: diff --git a/target/arm/translate.h b/target/arm/translate.h index dd24f91f26..3760159661 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -124,7 +124,7 @@ static inline int default_exception_el(DisasContext *s) * exceptions can only be routed to ELs above 1, so we target the higher of * 1 or the current EL. */ - return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3) + return (s->mmu_idx == ARMMMUIdx_SE0 && s->secure_routed_to_el3) ? 3 : MAX(1, s->current_el); } diff --git a/target/arm/helper.c b/target/arm/helper.c index a34accec20..377825431a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3144,7 +3144,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) mmu_idx = ARMMMUIdx_Stage1_E1; break; case 1: - mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; break; default: g_assert_not_reached(); @@ -3154,13 +3154,13 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ switch (el) { case 3: - mmu_idx = ARMMMUIdx_S1SE0; + mmu_idx = ARMMMUIdx_SE0; break; case 2: mmu_idx = ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx = secure ? ARMMMUIdx_SE0 : ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3214,7 +3214,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; + mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx = ARMMMUIdx_S1E2; @@ -3227,13 +3227,13 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; + mmu_idx = secure ? ARMMMUIdx_SE0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_EL10_1; + mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_EL10_1; break; case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_EL10_0; + mmu_idx = secure ? ARMMMUIdx_SE0 : ARMMMUIdx_EL10_0; break; default: g_assert_not_reached(); @@ -3895,7 +3895,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env, static int vae1_tlbmask(CPUARMState *env) { if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; } else { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0; } @@ -3931,7 +3931,7 @@ static int vmalle1_tlbmask(CPUARMState *env) * stage 1 translations. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_Stage2; } else { @@ -8569,9 +8569,9 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) return 2; case ARMMMUIdx_S1E3: return 3; - case ARMMMUIdx_S1SE0: + case ARMMMUIdx_SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; - case ARMMMUIdx_S1SE1: + case ARMMMUIdx_SE1: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_MPrivNegPri: @@ -8710,7 +8710,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { - case ARMMMUIdx_S1SE0: + case ARMMMUIdx_SE0: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: @@ -11150,7 +11150,7 @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) } if (el < 2 && arm_is_secure_below_el3(env)) { - return ARMMMUIdx_S1SE0 + el; + return ARMMMUIdx_SE0 + el; } else { return ARMMMUIdx_EL10_0 + el; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3a39315a6c..885c99f0c9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -116,8 +116,8 @@ static inline int get_a64_user_mem_index(DisasContext *s) case ARMMMUIdx_EL10_1: useridx = ARMMMUIdx_EL10_0; break; - case ARMMMUIdx_S1SE1: - useridx = ARMMMUIdx_S1SE0; + case ARMMMUIdx_SE1: + useridx = ARMMMUIdx_SE0; break; case ARMMMUIdx_Stage2: g_assert_not_reached(); diff --git a/target/arm/translate.c b/target/arm/translate.c index 1716bbb615..787e34f258 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -157,9 +157,9 @@ static inline int get_a32_user_mem_index(DisasContext *s) case ARMMMUIdx_EL10_1: return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0); case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: - return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0); + case ARMMMUIdx_SE0: + case ARMMMUIdx_SE1: + return arm_to_core_mmu_idx(ARMMMUIdx_SE0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: return arm_to_core_mmu_idx(ARMMMUIdx_MUser);