From patchwork Tue Nov 19 14:12:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 179762 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp706072ilf; Tue, 19 Nov 2019 06:24:03 -0800 (PST) X-Google-Smtp-Source: APXvYqzsNuvpe3XDY4Yu1ydZeM0KlRag5Iav7nqyiUfe1ii3cTlrSayrCOXeAXMggm4OmyC5q8CS X-Received: by 2002:ac8:118d:: with SMTP id d13mr33201176qtj.249.1574173443708; Tue, 19 Nov 2019 06:24:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574173443; cv=none; d=google.com; s=arc-20160816; b=gessnwY2jgThqJ0Bwi3Q5wIi4rkLQf5vwyLb00h3qpprx23NAZJJF4WhOKeIbEulUK YQk9bq8Crg1VENXlETZMv43E84eR3JEr30emNu1xKRtSE4XwlU1l1+SvQhqa9HbzBWzw buECPflINFmo7uHkl+TDbqij6VnAb2bGUMzosWsifuyVOu2LgkjSMAwgCn5EXg3fy60N 1s+39X6NOl9gmI7BmLDwY931qS6/My75zygfhfbIpVWFlaaJ59vzIq+f4rJOSo9GvHFG zkI1wOWNzVoGXGm6LjIqhOTueibqP3KmpUaQiG4mifdINtO5jbeSZqO36CrZ3LrBq0WS gkiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=leWo8XBnS/d7vN61dRYnOAncbw+pMzfCkH2LRBkyqwE=; b=AHDjq7heR61QnVGlxqN8U6iWUCAn6XMaDDlPalev4M8yM/1gScZ+j//AjBy1XyvsoU qazH88v2qxvTGAdP6avXxwThO4FOVUvORK+LmqDK+jiUdXSaw2zTP9g6TtdOcNjEyXoP 9R0TVYoSUuatT4CNu6cF0IInizDkwE5oQAfwJWsVojM7bnZfZ26l3XVIn5dh5rxsVkIh r/brrp9OU6uIgh+dSRg9VJH2kHNv8o5V2zbLi45MwXc07aIeIzbOEn+ZEgfDeYYZBed2 JBKH0DQfhgliOVOhCJM1P9axcNalInGSf1l82QyW4etywU9Z8JTgtK+VrOAkKZYBcQz1 02Fg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g40si13628363qtk.252.2019.11.19.06.24.03 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Nov 2019 06:24:03 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:46056 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX4QE-0001cx-HI for patch@linaro.org; Tue, 19 Nov 2019 09:24:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42005) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iX4Fy-0006Qp-L7 for qemu-devel@nongnu.org; Tue, 19 Nov 2019 09:13:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iX4Fw-0005R3-Hb for qemu-devel@nongnu.org; Tue, 19 Nov 2019 09:13:26 -0500 Received: from 5.mo1.mail-out.ovh.net ([178.33.45.107]:60327) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iX4Fv-0005Po-Hu for qemu-devel@nongnu.org; Tue, 19 Nov 2019 09:13:24 -0500 Received: from player795.ha.ovh.net (unknown [10.108.57.211]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 85C9319BC9B for ; Tue, 19 Nov 2019 15:13:20 +0100 (CET) Received: from kaod.org (deibp9eh1--blueice1n4.emea.ibm.com [195.212.29.166]) (Authenticated sender: clg@kaod.org) by player795.ha.ovh.net (Postfix) with ESMTPSA id 9BA1DC18AAE1; Tue, 19 Nov 2019 14:13:12 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: Peter Maydell Subject: [PATCH 07/17] aspeed/scu: Fix W1C behavior Date: Tue, 19 Nov 2019 15:12:01 +0100 Message-Id: <20191119141211.25716-8-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191119141211.25716-1-clg@kaod.org> References: <20191119141211.25716-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 17906312122056477457 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudegkedgiedvucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdqfffguegfifdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepveorughrihgtucfnvgcuifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucfkpheptddrtddrtddrtddpudelhedrvdduvddrvdelrdduieeinecurfgrrhgrmhepmhhouggvpehsmhhtphdqohhuthdphhgvlhhopehplhgrhigvrhejleehrdhhrgdrohhvhhdrnhgvthdpihhnvghtpedtrddtrddtrddtpdhmrghilhhfrhhomheptghlgheskhgrohgurdhorhhgpdhrtghpthhtohepqhgvmhhuqdguvghvvghlsehnohhnghhnuhdrohhrghenucevlhhushhtvghrufhiiigvpeef X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 178.33.45.107 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Alex_Benn=C3=A9e?= , Joel Stanley Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley This models the clock write one to clear registers, and fixes up some incorrect behavior in all of the write to clear registers. There was also a typo in one of the register definitions. Reviewed-by: Cédric Le Goater Reviewed-by: Alex Bennée Signed-off-by: Joel Stanley [clg: checkpatch.pl fixes ] Signed-off-by: Cédric Le Goater --- hw/misc/aspeed_scu.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) -- 2.21.0 diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 717509bc5460..f62fa25e3474 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -98,7 +98,7 @@ #define AST2600_CLK_STOP_CTRL TO_REG(0x80) #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84) #define AST2600_CLK_STOP_CTRL2 TO_REG(0x90) -#define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94) +#define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94) #define AST2600_SDRAM_HANDSHAKE TO_REG(0x100) #define AST2600_HPLL_PARAM TO_REG(0x200) #define AST2600_HPLL_EXT TO_REG(0x204) @@ -532,11 +532,13 @@ static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset, return s->regs[reg]; } -static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint64_t data, - unsigned size) +static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, + uint64_t data64, unsigned size) { AspeedSCUState *s = ASPEED_SCU(opaque); int reg = TO_REG(offset); + /* Truncate here so bitwise operations below behave as expected */ + uint32_t data = data64; if (reg >= ASPEED_AST2600_SCU_NR_REGS) { qemu_log_mask(LOG_GUEST_ERROR, @@ -563,15 +565,22 @@ static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint64_t data, /* fall through */ case AST2600_SYS_RST_CTRL: case AST2600_SYS_RST_CTRL2: + case AST2600_CLK_STOP_CTRL: + case AST2600_CLK_STOP_CTRL2: /* W1S (Write 1 to set) registers */ s->regs[reg] |= data; return; case AST2600_SYS_RST_CTRL_CLR: case AST2600_SYS_RST_CTRL2_CLR: + case AST2600_CLK_STOP_CTRL_CLR: + case AST2600_CLK_STOP_CTRL2_CLR: case AST2600_HW_STRAP1_CLR: case AST2600_HW_STRAP2_CLR: - /* W1C (Write 1 to clear) registers */ - s->regs[reg] &= ~data; + /* + * W1C (Write 1 to clear) registers are offset by one address from + * the data register + */ + s->regs[reg - 1] &= ~data; return; case AST2600_RNG_DATA: