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[209.51.188.17]) by mx.google.com with ESMTPS id f29si11102404ejj.110.2019.10.14.04.21.26 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 Oct 2019 04:21:26 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=tOsfDhQr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47614 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iJyPl-0006Re-IO for patch@linaro.org; Mon, 14 Oct 2019 07:21:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45469) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iJy29-0006a7-Le for qemu-devel@nongnu.org; Mon, 14 Oct 2019 06:57:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iJy28-00058d-7P for qemu-devel@nongnu.org; Mon, 14 Oct 2019 06:57:01 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:34513) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iJy28-00055D-1D for qemu-devel@nongnu.org; Mon, 14 Oct 2019 06:57:00 -0400 Received: by mail-wm1-x342.google.com with SMTP id y135so14227037wmc.1 for ; Mon, 14 Oct 2019 03:56:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+MF52Dp1tIuy0gH0L5TXn68Hzokx6/nbmqPRJPtyksM=; b=tOsfDhQrvWGnrPVlnmK5f/TXut0hgwt19BVb3kVnHdg7JIntLwUKOuGk3Fex87sNFR ua29FaRJ944GmxxOQ//ypy/qqlukJYMb3mqxVyFDroPTMLD2u4depBlyruhBXYiQw2tF If+TmHeHP7dXxUZGmdTVVOkDbXJapok2RhVK7TXwF+N+eekRisc+jBBAfKI2m+O2yeXq Zs+VKBsLO07sGKafYHMMOqdG98VV6tT8/G8ABwQmlILJpT7IycWM7sxEoIRvemobI+TR JHriRBpULPNIr3vyWfS6UXitMRyfxj+l/NjwnbOqaf5GZgVOtqozjEHQn4n8mvVSCJB7 BCkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+MF52Dp1tIuy0gH0L5TXn68Hzokx6/nbmqPRJPtyksM=; b=BWDYqjjukhMUdkAQsmIKwO17aKW0maedFRfJtknrTmK6N3Ez6l13iQ5BzsIyoU8mtJ 1wRuJPSg1KCVwdCh0spN0JodpXlifh8ZnH5B1ewUJKHKZ1MBSgHFKCPNOdh0c1vDUgI1 zeGw8tY0ADvfN5btbvCZEHMbJxTkdVrM8/AHE0RRKixbEoZgN6587JRmidDxdO5VSAik 5QwszCYsN5lgzVqrok3tXSpMPbSV2X/26jwEJOkhpF1PbDW4ELKCCGSCKXuyf4YhW9QN avaEziep76TYm8ufcMw9YCisivJnNh5xpup2QONCxLiutajegRTpD3/z7g/yrrTjecRN kCwg== X-Gm-Message-State: APjAAAUCZmCgBLty2hd2wZyYkAIj0rpSL16uko05dSnj1O29CKG/h4jT rF8hUU+7f+pxvQ1ATfnHFakejifz4tU= X-Received: by 2002:a1c:41c1:: with SMTP id o184mr15324749wma.81.1571050617771; Mon, 14 Oct 2019 03:56:57 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id f13sm16009547wmj.17.2019.10.14.03.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Oct 2019 03:56:56 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 30E8C1FF8C; Mon, 14 Oct 2019 11:49:56 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v5 31/55] target/riscv: fetch code with translator_ld Date: Mon, 14 Oct 2019 11:49:24 +0100 Message-Id: <20191014104948.4291-32-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191014104948.4291-1-alex.bennee@linaro.org> References: <20191014104948.4291-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V TCG CPUs" , Sagar Karandikar , Bastian Koppelmann , robert.foley@futurewei.com, Palmer Dabbelt , Richard Henderson , peter.puhov@futurewei.com, aaron@os.amperecomputing.com, cota@braap.org, Alistair Francis , =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Signed-off-by: Emilio G. Cota Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- target/riscv/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Alistair Francis Acked-by: Palmer Dabbelt diff --git a/target/riscv/translate.c b/target/riscv/translate.c index adeddb85f6..b26533d4fd 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -779,7 +779,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) DisasContext *ctx = container_of(dcbase, DisasContext, base); CPURISCVState *env = cpu->env_ptr; - ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); + ctx->opcode = translator_ldl(env, ctx->base.pc_next); decode_opc(ctx); ctx->base.pc_next = ctx->pc_succ_insn;