From patchwork Fri Oct 11 13:47:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175951 Delivered-To: patch@linaro.org Received: by 2002:ac9:3c86:0:0:0:0:0 with SMTP id w6csp961177ocf; Fri, 11 Oct 2019 06:51:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqzmHqQhL4wfLN+D2FCjBuC/Wm3WeAkXAKotUq3S5/OOjUZ8eLyuEYi59Xce3oxbTv/pWG49 X-Received: by 2002:a50:ee92:: with SMTP id f18mr14027730edr.56.1570801911671; Fri, 11 Oct 2019 06:51:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570801911; cv=none; d=google.com; s=arc-20160816; b=SaVX0Mp+gnrP4S7TINJJb/2yiNRR/o6mdgs+ix1tXcTWETCmS9ziUadLqt/t1i56Gp rNd5A3NbD6LDlQ0FWqdDJajItJL2s/1YJSPMt7Jkr9xhHL51vbE/vH5LMg0m921ASuKk fLeEl5/ncTUuEJOwCJrGg+w88ZiLB5Jbj7IXOX5tA9wjQpesCBVaH/ykAP29oCdCIkzr btalMkDf+vLD0XUCLW6auRbCM6PMtw4WsjJsuUWfPdGmMDsgKGUrn8uxL0VaaJahHb8/ 5fmR5roSodhrEz2Yf7wpcNa2Di7PM79a/xRpBacvIzBF6qgyOryGI3fX/bFQ5zxo/5VT G9gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:references:in-reply-to :message-id:date:subject:to:from:dkim-signature; bh=u6kz9NuK9Wp4TrtRthl3Manwia2sE3vhzut21VwbSSg=; b=kPHwcx2kWdaDLi1+7QMJn8l55G7LbFtH5owOFla0vhLenDpIwUUNRu6/Kb5J4GntJh zoJzwH4SCMoBWW5EHI+4Y/Wa41DVBK8xPBm+x9maO7Ay/7Y6MGxncCq1VhewKapREP1k zUa9uZIpszkCda1wH31CUl0XrOFeTku8G8FK2FJyEj8+w1ZyRK8gtYzpUtaoYO01N5Ut o29G0839Vd2UxxDYBjAYHypV5qWfIqkrAvsaDnNgL24bZM5mCmjiIxOSXLxNS80Vc3e+ SeMzwpe72XlTKkHhGhpvpKOdCqUh8RLhdpQlowxxJ6KSA7vs6bpC2oukcefnOL6phVhY F9hA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WI5AX+15; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p20si5165658ejg.30.2019.10.11.06.51.51 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 11 Oct 2019 06:51:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WI5AX+15; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50552 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIvKg-0006GZ-1B for patch@linaro.org; Fri, 11 Oct 2019 09:51:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38670) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIvHt-0003d6-OL for qemu-devel@nongnu.org; Fri, 11 Oct 2019 09:48:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iIvHs-0003Nj-FC for qemu-devel@nongnu.org; Fri, 11 Oct 2019 09:48:57 -0400 Received: from mail-yw1-xc43.google.com ([2607:f8b0:4864:20::c43]:34902) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iIvHs-0003N4-Bb for qemu-devel@nongnu.org; Fri, 11 Oct 2019 09:48:56 -0400 Received: by mail-yw1-xc43.google.com with SMTP id r134so3500984ywg.2 for ; Fri, 11 Oct 2019 06:48:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u6kz9NuK9Wp4TrtRthl3Manwia2sE3vhzut21VwbSSg=; b=WI5AX+15EMrGSqPRoSd9m1GVeMzKoIv+IbLNVd57Ti9Qhf7ii5bNn1Gr0f2BXh7JQl O3bciESry5V3pSdA4VExdKm+skOnrLcIUbyyicYjy/CDTGlZtPHtOi/VP+dtZXHFZDzo yp4+kzdHIPz7Nolj9N0l6DBQN+64oBISD+WYi4dFjrWzIwRz1JnLNt0Ad+92ivX/RJJl SVLqEL7c+XtZaeVDmUbwhtokaEdbB7oif71SrC862ricsdPbGh+PSLG4poKXOsFxafdN SbbpiO5sm1HCZiihBQNvVg8NZ1j00O3JJ5YLNotKJZaRBFhCRFrUH+aJ5tooe+s5nIQi dNYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u6kz9NuK9Wp4TrtRthl3Manwia2sE3vhzut21VwbSSg=; b=Llh2xJOj/N1dtfR2GTsXGXZ3HoVI66vhAilkH0omzGuuphEqTf7p7myoPcU/GgUmn+ qxYDQeWppS9Tn14UvFmF7l+M0U9dEUVWOuD+iEt/Aljua8E3hL/lpzArjo/2YP45w/En AlBxgDLganAn6XqAI3hXTUomUV4Ee4afUv9cY3lqEp1zLAkq4bnHh5IxvJeKPtr2KfS2 lhgTdt/1GiFg8UkDuNjFnDLPmqBA1RwlazUeTyoi3V0WzZlexwPDAdP6Nsg1mXT9xwmH pbQ1R6qC2dTQsIjjoG3QVYKbyemZYVrAMWbH+UE+SSbGMjpdLARpocCtl+KaerokEba8 qpJg== X-Gm-Message-State: APjAAAU+ira1unB6rrcPZ87Tuo5jLe1yEQ83qlNDEHUMwAVo7BlcEvEU BEJUBSNNgTGF0LUV6rvxfDVkgA80CqU= X-Received: by 2002:a81:688a:: with SMTP id d132mr2314569ywc.452.1570801735166; Fri, 11 Oct 2019 06:48:55 -0700 (PDT) Received: from cloudburst.gateway.pace.com (67.216.151.25.pool.hargray.net. [67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.48.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:48:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 03/22] target/arm: Add MTE system registers Date: Fri, 11 Oct 2019 09:47:25 -0400 Message-Id: <20191011134744.2477-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO. Signed-off-by: Richard Henderson --- v3: Add GMID; add access_mte. v4: Define only TCO at mte_insn_reg. --- target/arm/cpu.h | 3 ++ target/arm/internals.h | 6 ++++ target/arm/helper.c | 73 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 11 ++++++ 4 files changed, 93 insertions(+) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 408d749b7a..d99bb5e956 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -486,6 +486,9 @@ typedef struct CPUARMState { uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ + uint64_t tfsr_el[4]; /* tfsrel0_el1 is index 0. */ + uint64_t gcr_el1; + uint64_t rgsr_el1; } cp15; struct { diff --git a/target/arm/internals.h b/target/arm/internals.h index 9486680b87..bfa243be06 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1079,4 +1079,10 @@ void arm_log_exception(int idx); #endif /* !CONFIG_USER_ONLY */ +/* + * The log2 of the words in the tag block, for GMID_EL1.BS. + * The is the maximum, 256 bytes, which manipulates 64-bits of tags. + */ +#define GMID_EL1_BS 6 + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index f9dee51ede..f435a8d8bd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5921,6 +5921,73 @@ static const ARMCPRegInfo rndr_reginfo[] = { .access = PL0_R, .readfn = rndr_readfn }, REGINFO_SENTINEL }; + +static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el = arm_current_el(env); + + if (el < 2 && + arm_feature(env, ARM_FEATURE_EL2) && + !(arm_hcr_el2_eff(env) & HCR_ATA)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && + arm_feature(env, ARM_FEATURE_EL3) && + !(env->cp15.scr_el3 & SCR_ATA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_TCO; +} + +static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) +{ + env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); +} + +static const ARMCPRegInfo mte_reginfo[] = { + { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 6, .crm = 6, .opc2 = 1, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, + { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 6, .crm = 5, .opc2 = 0, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, + { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 5, .opc2 = 0, + .access = PL2_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, + { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 6, .opc2 = 0, + .access = PL3_RW, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, + { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, + { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, + .access = PL1_RW, .accessfn = access_mte, + .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, + { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo mte_tco_reginfo[] = { + { .name = "TCO", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, + .type = ARM_CP_NO_RAW, + .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, + REGINFO_SENTINEL +}; #endif static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, @@ -6881,6 +6948,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_rndr, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } + if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { + define_arm_cp_regs(cpu, mte_tco_reginfo); + } + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, mte_reginfo); + } #endif /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c85db69db4..62bdf50796 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1611,6 +1611,17 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, s->base.is_jmp = DISAS_UPDATE; break; + case 0x1c: /* TCO */ + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_TCO); + } else { + clear_pstate_bits(PSTATE_TCO); + } + break; + default: do_unallocated: unallocated_encoding(s);