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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id f68sm2534000ywb.96.2019.10.11.06.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 06:50:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 22/22] target/arm: Add allocation tag storage for system mode Date: Fri, 11 Oct 2019 09:47:44 -0400 Message-Id: <20191011134744.2477-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191011134744.2477-1-richard.henderson@linaro.org> References: <20191011134744.2477-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 61 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) -- 2.17.1 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index e8d8a6bedb..657383ba0e 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -28,8 +28,69 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, uint64_t ptr, bool write, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY /* Tag storage not implemented. */ return NULL; +#else + CPUState *cs = env_cpu(env); + uintptr_t index; + int mmu_idx; + CPUTLBEntry *entry; + CPUIOTLBEntry *iotlbentry; + MemoryRegionSection *section; + hwaddr physaddr, tag_physaddr; + + /* + * Find the TLB entry for this access. + * As a side effect, this also raises an exception for invalid access. + * + * TODO: Perhaps there should be a cputlb helper that returns a + * matching tlb entry + iotlb entry. That would also be able to + * make use of the victim tlb cache, which is currently private. + */ + mmu_idx = cpu_mmu_index(env, false); + index = tlb_index(env, mmu_idx, ptr); + entry = tlb_entry(env, mmu_idx, ptr); + if (!tlb_hit(write ? tlb_addr_write(entry) : entry->addr_read, ptr)) { + bool ok = arm_cpu_tlb_fill(cs, ptr, 16, + write ? MMU_DATA_STORE : MMU_DATA_LOAD, + mmu_idx, false, ra); + assert(ok); + index = tlb_index(env, mmu_idx, ptr); + entry = tlb_entry(env, mmu_idx, ptr); + } + + /* If the virtual page MemAttr != Tagged, nothing to do. */ + iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index]; + if (!iotlbentry->attrs.target_tlb_bit1) { + return NULL; + } + + /* + * Find the physical address for the virtual access. + * + * TODO: It should be possible to have the tag mmu_idx map + * from main memory ram_addr to tag memory host address. + * that would allow this lookup step to be cached as well. + */ + section = iotlb_to_section(cs, iotlbentry->addr, iotlbentry->attrs); + physaddr = ((iotlbentry->addr & TARGET_PAGE_MASK) + ptr + + section->offset_within_address_space + - section->offset_within_region); + + /* Convert to the physical address in tag space. */ + tag_physaddr = physaddr >> (LOG2_TAG_GRANULE + 1); + + /* Choose the tlb index to use for the tag physical access. */ + mmu_idx = iotlbentry->attrs.secure ? ARMMMUIdx_TagS : ARMMMUIdx_TagNS; + mmu_idx = arm_to_core_mmu_idx(mmu_idx); + + /* + * FIXME: Get access length and type so that we can use + * probe_access, so that pages are marked dirty for migration. + */ + return tlb_vaddr_to_host(env, tag_physaddr, MMU_DATA_LOAD, mmu_idx); +#endif } static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra)