From patchwork Thu Oct 10 11:33:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Hildenbrand X-Patchwork-Id: 175763 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp2171995ill; Thu, 10 Oct 2019 04:50:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqxWOebgVGGoH1KskEKT8q/uwMjtqRhpPS6/XEthEbA6dAdAppupJ3jQeCMRLS/DyNuRzJkx X-Received: by 2002:a37:9343:: with SMTP id v64mr8711747qkd.241.1570708230173; Thu, 10 Oct 2019 04:50:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570708230; cv=none; d=google.com; s=arc-20160816; b=w/A/MYzrmZjW3lKuPty7cI7HBe9p/wfLK05haPcnZ/YQPacZQ2z2hDi87NAdzOlmo4 YMSdQcQLOZNXPO2oNO05cXk1xWcPsAAPpFa/kkzS5ZWqBhRGDxeAhadS+Xi4hRNH02HL OewhXljHZomBkvgx9YGrEpLwUqNJJFfjYtNJILytalaH+IXe6lnAvbICeax8vPBiN6KF vKTbP+RVFMhymsvZq/02asgb7DE+3qOuW7Uv31Aj8fp+YGrlG7lQkqJK+nmO5Nq30mRT WUglpxf3jMW/gqhGbA0QomqKpu6D3bSDqSOm3dqFWY/mK6MBrA86hT6SjNT5PjSmDhnC uGTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from; bh=7qe0U0PsyzruDmGkne0ZlXjxfeTvUUHGZ291y/GWCHg=; b=mDTYnRnce32hiknThy5Vv+eenKgYNPJbgbv4ZmiqkKTOFtWSCW846jlXa3UlsCJGWk ikO0sLsxveSJCBwnn+x8azNni+mlJxm2QJuhF7bjHQlgmOkbBRjEhyEIvn8RrVX0P5Uj IW5aNgkF78hjPuf6r6dt/l/VgYM3gRvp5GMyef3/hyeeNG5Y9eTF/+ik7b6PgPj338gc 0K+NbiJoYIPZe2nxlzJ+FA7CtUZOSbI1lVZADIgXSJuvqIJtHFA3NOri4fnfdDlzLjuF sMgrlnOC8KdSdXFouh9GMdj6TS1p39SJZ9axCY1N6NAdT5zv8M+1OxkD9oppj7CPx0SI 2tXA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v34si5420154qtd.70.2019.10.10.04.50.30 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 Oct 2019 04:50:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1]:36698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIWxh-0003sD-BL for patch@linaro.org; Thu, 10 Oct 2019 07:50:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50424) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iIWj3-0004Sj-HR for qemu-devel@nongnu.org; Thu, 10 Oct 2019 07:35:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iIWj1-00067k-Gg for qemu-devel@nongnu.org; Thu, 10 Oct 2019 07:35:21 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52128) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iIWiz-00064I-EJ; Thu, 10 Oct 2019 07:35:19 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 9BFE37CB95; Thu, 10 Oct 2019 11:35:09 +0000 (UTC) Received: from t460s.redhat.com (ovpn-117-138.ams2.redhat.com [10.36.117.138]) by smtp.corp.redhat.com (Postfix) with ESMTP id 98EA95E1B0; Thu, 10 Oct 2019 11:35:03 +0000 (UTC) From: David Hildenbrand To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 18/31] target/s390x: Handle tec in s390_cpu_tlb_fill Date: Thu, 10 Oct 2019 13:33:43 +0200 Message-Id: <20191010113356.5017-19-david@redhat.com> In-Reply-To: <20191010113356.5017-1-david@redhat.com> References: <20191010113356.5017-1-david@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Thu, 10 Oct 2019 11:35:09 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-s390x@nongnu.org, Cornelia Huck , Richard Henderson , Thomas Huth , David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson As a step toward moving all excption handling out of mmu_translate, copy handling of the LowCore tec value from trigger_access_exception into s390_cpu_tlb_fill. So far this new plumbing isn't used. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson Message-Id: <20191001171614.8405-7-richard.henderson@linaro.org> Signed-off-by: David Hildenbrand --- target/s390x/excp_helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.21.0 diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index 552098be5f..ab2ed47fef 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -126,7 +126,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, S390CPU *cpu = S390_CPU(cs); CPUS390XState *env = &cpu->env; target_ulong vaddr, raddr; - uint64_t asc; + uint64_t asc, tec; int prot, fail, excp; qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %d\n", @@ -162,6 +162,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, "%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__, (uint64_t)raddr, (uint64_t)ram_size); excp = PGM_ADDRESSING; + tec = 0; /* unused */ fail = 1; } @@ -178,6 +179,10 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } if (excp) { + if (excp != PGM_ADDRESSING) { + stq_phys(env_cpu(env)->as, + env->psa + offsetof(LowCore, trans_exc_code), tec); + } trigger_pgm_exception(env, excp, ILEN_AUTO); } cpu_restore_state(cs, retaddr, true);