@@ -127,7 +127,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
CPUS390XState *env = &cpu->env;
target_ulong vaddr, raddr;
uint64_t asc;
- int prot, fail;
+ int prot, fail, excp;
qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
@@ -141,12 +141,14 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
vaddr &= 0x7fffffff;
}
fail = mmu_translate(env, vaddr, access_type, asc, &raddr, &prot, true);
+ excp = 0; /* exception already raised */
} else if (mmu_idx == MMU_REAL_IDX) {
/* 31-Bit mode */
if (!(env->psw.mask & PSW_MASK_64)) {
vaddr &= 0x7fffffff;
}
fail = mmu_translate_real(env, vaddr, access_type, &raddr, &prot);
+ excp = 0; /* exception already raised */
} else {
g_assert_not_reached();
}
@@ -159,7 +161,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU,
"%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n",
__func__, (uint64_t)raddr, (uint64_t)ram_size);
- trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
+ excp = PGM_ADDRESSING;
fail = 1;
}
@@ -175,6 +177,9 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
return false;
}
+ if (excp) {
+ trigger_pgm_exception(env, excp, ILEN_AUTO);
+ }
cpu_restore_state(cs, retaddr, true);
/*