@@ -127,7 +127,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
CPUS390XState *env = &cpu->env;
target_ulong vaddr, raddr;
uint64_t asc, tec;
- int prot, fail, excp;
+ int prot, excp;
qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
@@ -141,20 +141,18 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
vaddr &= 0x7fffffff;
}
excp = mmu_translate(env, vaddr, access_type, asc, &raddr, &prot, &tec);
- fail = excp;
} else if (mmu_idx == MMU_REAL_IDX) {
/* 31-Bit mode */
if (!(env->psw.mask & PSW_MASK_64)) {
vaddr &= 0x7fffffff;
}
excp = mmu_translate_real(env, vaddr, access_type, &raddr, &prot, &tec);
- fail = excp;
} else {
g_assert_not_reached();
}
/* check out of RAM access */
- if (!fail &&
+ if (!excp &&
!address_space_access_valid(&address_space_memory, raddr,
TARGET_PAGE_SIZE, access_type,
MEMTXATTRS_UNSPECIFIED)) {
@@ -163,10 +161,9 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
__func__, (uint64_t)raddr, (uint64_t)ram_size);
excp = PGM_ADDRESSING;
tec = 0; /* unused */
- fail = 1;
}
- if (!fail) {
+ if (!excp) {
qemu_log_mask(CPU_LOG_MMU,
"%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n",
__func__, (uint64_t)vaddr, (uint64_t)raddr, prot);
@@ -178,13 +175,11 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
return false;
}
- if (excp) {
- if (excp != PGM_ADDRESSING) {
- stq_phys(env_cpu(env)->as,
- env->psa + offsetof(LowCore, trans_exc_code), tec);
- }
- trigger_pgm_exception(env, excp, ILEN_AUTO);
+ if (excp != PGM_ADDRESSING) {
+ stq_phys(env_cpu(env)->as,
+ env->psa + offsetof(LowCore, trans_exc_code), tec);
}
+ trigger_pgm_exception(env, excp, ILEN_AUTO);
cpu_restore_state(cs, retaddr, true);
/*