From patchwork Tue Sep 24 21:00:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 174306 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp4665527ill; Tue, 24 Sep 2019 14:08:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqwju3QWEbYbuf8/Xxzzhdi5mrU2nXwkV9VS37iz/1X3SGl9D9/7ip9QuHJ4oLZzKoWgqwlk X-Received: by 2002:a37:4a0c:: with SMTP id x12mr103456qka.23.1569359327178; Tue, 24 Sep 2019 14:08:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569359327; cv=none; d=google.com; s=arc-20160816; b=U9hZlaHQL3IEbrqBhj4BJGzsEKHqJjPbUKD1zmID3BoudCBYcRCfZG6HJ0mcYXvG2W DLwjn1Bo2yloXTjfaMvdYNeGQEZ++VhlF6kN4QCUIvmL4ZQkSpoMVeQsmHFXdyoJW1aH DDXkN4sdxOh+N4bw2D8gVkApzSiWnT9+fpHCxLX3b447uLttByydPvDmOCDd/qH3HiHG BB9VDI+DVmvP7VdtXnty+SLXis/eCfx4j7TyedHXPiKBBJ4nu1LFcoaML0QcnKocxFsD Oo6x0lH2Q1AgTT7u7BK9VEFRl6b5YWbJ+3ccXgQVtpYCSutZL1Q1VbgKk6S/r4OG1r2S 9aYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Ga7uunm/945QAukjyLgeNBXLoqr7gtD7KgepZs9QTXE=; b=DZZulJ2dZHdF8r1u8XeQL9s4RaqsadN1Iwry2ToRVMMY5Y99wgGLest5MzwKzSSCXx ZQ6p2mb2QbCcrfY7sZJv5AzrCHa4iBSxWDLOMhVK0c8kjpOo5PpQmOcJOwE/kbLryk56 v80udE9cB91HMCxrJoFDc/LhsXYvBMycuE8xn4OXnGXH12XJvaFhycJIs1u2gVJOtPjd yw6r523Nk55ytAstJF6WnQC38QV9thfNb0/fswRqEKUgW/Jv5iTCeQSQ2610iXvwB5ft 1F9GO3YEQMmswp1nDLa8k7eLVyWnbIh9bWqWgrhbXkRdKPK3ye4xqi1Ukgm0gM3Gr+/J n8CA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=THY2tt0w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g184si2206939qkf.290.2019.09.24.14.08.47 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 24 Sep 2019 14:08:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=THY2tt0w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCs3B-00088K-UY for patch@linaro.org; Tue, 24 Sep 2019 17:08:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55499) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iCrw0-0002XQ-RF for qemu-devel@nongnu.org; Tue, 24 Sep 2019 17:01:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iCrvy-0004Tr-K8 for qemu-devel@nongnu.org; Tue, 24 Sep 2019 17:01:20 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:33517) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iCrvv-0004S9-2e for qemu-devel@nongnu.org; Tue, 24 Sep 2019 17:01:17 -0400 Received: by mail-wm1-x342.google.com with SMTP id r17so2494174wme.0 for ; Tue, 24 Sep 2019 14:01:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ga7uunm/945QAukjyLgeNBXLoqr7gtD7KgepZs9QTXE=; b=THY2tt0w+DowVHywlbF5pOM+PuCes/RILuoRPdQiVA3hvhUM7gRSi8L4I/84USKrTg 22LDMceo+S3M4I12vHAwPzS7QuQCIVRssZI3Z65Db6ht8gjv4q/D06gJm3YIfxHwoYnP mAoWxS7wdxPzuLnwOb8lfUCYTf18IAivX/bO/Qw344Z8C/fe3366F6ktPGxZ0cQXkuGv LXDTs9eOIdp3OB5i4UOZ3B3S2ivDLadn9IjEUc3jQ+wbdsAP8d5iEOhehDPmPAKxhS4r 8yxKK4OupLZr3EG0PkE5dnRWFWVug/rOitn62wjSwZ/Z/DkDLDYQJR3IeElWJPKm2OI0 xY8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ga7uunm/945QAukjyLgeNBXLoqr7gtD7KgepZs9QTXE=; b=pyBlA5gtmxhrb5HNceEr2m/zvjJgUQVQJT+X7BBNlAdwCdxpq/aH4B85TPQrDuwmKy wFkoFlCvM4RjD0gxA48Rkp4ZFgHBb2uQNIkn/BHLLYs/vA0dE7W4+sL5vQNBXF6ofqqr +/aKZGkRMprk5BwHkSe6Y7cbeL4dwGMdRmZZQOnxrfup90XqMwqXQwOLSXnU1B5B0Z08 86nJZrzS2k8fkgzsPTW200sOrpyZAY6HrDyRlL7Bd6xFxluQNlDpu85my+5hqDA0YDph pl8+ywKW+FZq76j7ywPiPnQMsRWuFItecP5FNDu/9T/gV+hFit/smlVGki3oo+gGtBIV 2NeA== X-Gm-Message-State: APjAAAUy0Np/x7/IKTRmKddbq6vcEk6zqCEt7hFQRUID4TwoR+geyRUa nYsP6B1hjvWbSLoI/QbLH82ACw== X-Received: by 2002:a7b:c0d4:: with SMTP id s20mr2585705wmh.101.1569358869962; Tue, 24 Sep 2019 14:01:09 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id y14sm4548491wrd.84.2019.09.24.14.01.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Sep 2019 14:01:08 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 21EE81FF90; Tue, 24 Sep 2019 22:01:07 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v3 03/33] target/alpha: Fix SWCR_TRAP_ENABLE_MASK Date: Tue, 24 Sep 2019 22:00:36 +0100 Message-Id: <20190924210106.27117-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190924210106.27117-1-alex.bennee@linaro.org> References: <20190924210106.27117-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , jsnow@redhat.com, f4bug@amsat.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The CONFIG_USER_ONLY adjustment blindly mashed the swcr exception enable bits into the fpcr exception disable bits. However, fpcr_exc_enable has already converted the exception disable bits into the exception status bits in order to make it easier to mask status bits at runtime. Instead, merge the swcr enable bits with the fpcr before we convert to status bits. Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée Message-Id: <20190921043256.4575-4-richard.henderson@linaro.org> --- target/alpha/helper.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 10602fb3394..e21c488aa32 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -46,34 +46,39 @@ void cpu_alpha_store_fpcr(CPUAlphaState *env, uint64_t val) uint32_t fpcr = val >> 32; uint32_t t = 0; + /* Record the raw value before adjusting for linux-user. */ + env->fpcr = fpcr; + +#ifdef CONFIG_USER_ONLY + /* + * Override some of these bits with the contents of ENV->SWCR. + * In system mode, some of these would trap to the kernel, at + * which point the kernel's handler would emulate and apply + * the software exception mask. + */ + uint32_t soft_fpcr = alpha_ieee_swcr_to_fpcr(env->swcr) >> 32; + fpcr |= soft_fpcr & FPCR_STATUS_MASK; +#endif + t |= CONVERT_BIT(fpcr, FPCR_INED, FPCR_INE); t |= CONVERT_BIT(fpcr, FPCR_UNFD, FPCR_UNF); t |= CONVERT_BIT(fpcr, FPCR_OVFD, FPCR_OVF); t |= CONVERT_BIT(fpcr, FPCR_DZED, FPCR_DZE); t |= CONVERT_BIT(fpcr, FPCR_INVD, FPCR_INV); - env->fpcr = fpcr; env->fpcr_exc_enable = ~t & FPCR_STATUS_MASK; env->fpcr_dyn_round = rm_map[(fpcr & FPCR_DYN_MASK) >> FPCR_DYN_SHIFT]; env->fpcr_flush_to_zero = (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ); env->fp_status.flush_inputs_to_zero = (fpcr & FPCR_DNZ) != 0; - #ifdef CONFIG_USER_ONLY - /* - * Override some of these bits with the contents of ENV->SWCR. - * In system mode, some of these would trap to the kernel, at - * which point the kernel's handler would emulate and apply - * the software exception mask. - */ if (env->swcr & SWCR_MAP_DMZ) { env->fp_status.flush_inputs_to_zero = 1; } if (env->swcr & SWCR_MAP_UMZ) { env->fpcr_flush_to_zero = 1; } - env->fpcr_exc_enable &= ~(alpha_ieee_swcr_to_fpcr(env->swcr) >> 32); #endif }