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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id n66sm8104610pfn.90.2019.09.04.13.45.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 13:45:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 13:45:06 -0700 Message-Id: <20190904204507.32457-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org> References: <20190904204507.32457-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::432 Subject: [Qemu-devel] [PULL 12/13] target/openrisc: Implement l.adrp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This was added to the 1.3 spec. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/disas.c | 1 + target/openrisc/translate.c | 13 +++++++++++++ target/openrisc/insns.decode | 2 ++ 3 files changed, 16 insertions(+) -- 2.17.1 diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c index e51cbb24c6..ce112640b9 100644 --- a/target/openrisc/disas.c +++ b/target/openrisc/disas.c @@ -98,6 +98,7 @@ INSN(sw, "%d(r%d), r%d", a->i, a->a, a->b) INSN(sb, "%d(r%d), r%d", a->i, a->a, a->b) INSN(sh, "%d(r%d), r%d", a->i, a->a, a->b) INSN(nop, "") +INSN(adrp, "r%d, %d", a->d, a->i) INSN(addi, "r%d, r%d, %d", a->d, a->a, a->i) INSN(addic, "r%d, r%d, %d", a->d, a->a, a->i) INSN(muli, "r%d, r%d, %d", a->d, a->a, a->i) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 6e8bc23568..6addbac8d6 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -799,6 +799,19 @@ static bool trans_l_nop(DisasContext *dc, arg_l_nop *a) return true; } +static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a) +{ + if (!check_v1_3(dc)) { + return false; + } + check_r0_write(dc, a->d); + + tcg_gen_movi_i32(cpu_R(dc, a->d), + (dc->base.pc_next & TARGET_PAGE_MASK) + + ((target_long)a->i << TARGET_PAGE_BITS)); + return true; +} + static bool trans_l_addi(DisasContext *dc, arg_rri *a) { TCGv t0; diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode index 71e0d740db..0d6f7c29f8 100644 --- a/target/openrisc/insns.decode +++ b/target/openrisc/insns.decode @@ -102,6 +102,8 @@ l_maci 010011 ----- a:5 i:s16 l_movhi 000110 d:5 ----0 k:16 l_macrc 000110 d:5 ----1 00000000 00000000 +l_adrp 000010 d:5 i:s21 + #### # Arithmetic Instructions ####