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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:54 -0700 Message-Id: <20190904193059.26202-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 64/69] target/arm: Convert T16, shift immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++------------------------ target/arm/t16.decode | 8 ++++++++ 2 files changed, 10 insertions(+), 24 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 48ed6f6b5d..d409afd55f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10754,7 +10754,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift; + uint32_t val, rd; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10766,29 +10766,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) /* fall back to legacy decoder */ switch (insn >> 12) { - case 0: case 1: - - rd = insn & 7; - op = (insn >> 11) & 3; - if (op == 3) { - /* - * 0b0001_1xxx_xxxx_xxxx - * - Add, subtract (three low registers) - * - Add, subtract (two low registers and immediate) - * In decodetree. - */ - goto illegal_op; - } else { - /* shift immediate */ - rm = (insn >> 3) & 7; - shift = (insn >> 6) & 0x1f; - tmp = load_reg(s, rm); - gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } - break; + case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ goto illegal_op; case 4: diff --git a/target/arm/t16.decode b/target/arm/t16.decode index f128110dee..79a1d66d6c 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -126,6 +126,14 @@ ADD_rri 10101 rd:3 ........ \ STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm +# Shift (immediate) + +@shift_i ..... shim:5 rm:3 rd:3 &s_rrr_shi %s rn=%reg_0 + +MOV_rxri 000 00 ..... ... ... @shift_i shty=0 # LSL +MOV_rxri 000 01 ..... ... ... @shift_i shty=1 # LSR +MOV_rxri 000 10 ..... ... ... @shift_i shty=2 # ASR + # Add/subtract (three low registers) @addsub_3 ....... rm:3 rn:3 rd:3 \