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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:44 -0700 Message-Id: <20190904193059.26202-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 54/69] target/arm: Convert T16 add, compare, move (two high registers) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 49 ++---------------------------------------- target/arm/t16.decode | 10 +++++++++ 2 files changed, 12 insertions(+), 47 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index e6ef935247..73c8863134 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10745,55 +10745,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) store_reg(s, rd, tmp); break; } - if (insn & (1 << 10)) { - /* 0b0100_01xx_xxxx_xxxx - * - data processing extended, branch and exchange - */ - rd = (insn & 7) | ((insn >> 4) & 8); - rm = (insn >> 3) & 0xf; - op = (insn >> 8) & 3; - switch (op) { - case 0: /* add */ - tmp = load_reg(s, rd); - tmp2 = load_reg(s, rm); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rd == 13) { - /* ADD SP, SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 1: /* cmp */ - tmp = load_reg(s, rd); - tmp2 = load_reg(s, rm); - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - break; - case 2: /* mov/cpy */ - tmp = load_reg(s, rm); - if (rd == 13) { - /* MOV SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 3: - /* 0b0100_0111_xxxx_xxxx - * - branch [and link] exchange thumb register - * In decodetree - */ - goto illegal_op; - } - break; - } /* - * 0b0100_00xx_xxxx_xxxx - * - Data-processing (two low registers), in decodetree + * - Data-processing (two low registers), in decodetree + * - data processing extended, branch and exchange, in decodetree */ goto illegal_op; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index edddbfb9b8..5a570484e3 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -146,6 +146,16 @@ CMP_xri 00101 ... ........ @arith_1i s=1 ADD_rri 00110 ... ........ @arith_1i %s SUB_rri 00111 ... ........ @arith_1i %s +# Add, compare, move (two high registers) + +%reg_0_7 7:1 0:3 +@addsub_2h .... .... . rm:4 ... \ + &s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0 + +ADD_rrri 0100 0100 . .... ... @addsub_2h s=0 +CMP_xrri 0100 0101 . .... ... @addsub_2h s=1 +MOV_rxri 0100 0110 . .... ... @addsub_2h s=0 + # Branch and exchange @branchr .... .... . rm:4 ... &r