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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:26 -0700 Message-Id: <20190904193059.26202-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 36/69] target/arm: Convert CPS (privileged) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Reject for m-profile; add TODO for unpredictable arguments. Sort the T32 decode adjacent to the hint space. --- target/arm/translate.c | 91 ++++++++++++++++-------------------- target/arm/a32-uncond.decode | 3 ++ target/arm/t32.decode | 5 ++ 3 files changed, 48 insertions(+), 51 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 364b51c2a6..664ea281f8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10145,6 +10145,44 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a) return true; } +static bool trans_CPS(DisasContext *s, arg_CPS *a) +{ + uint32_t mask, val; + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + /* Implemented as NOP in user mode. */ + return true; + } + /* TODO: There are quite a lot of UNPREDICTABLE argument combinations. */ + + mask = val = 0; + if (a->imod & 2) { + if (a->A) { + mask |= CPSR_A; + } + if (a->I) { + mask |= CPSR_I; + } + if (a->F) { + mask |= CPSR_F; + } + if (a->imod & 1) { + val |= mask; + } + } + if (a->M) { + mask |= CPSR_M; + val |= a->mode; + } + if (mask) { + gen_set_psr_im(s, mask, 0, val); + } + return true; +} + /* * Clear-Exclusive, Barriers */ @@ -10321,31 +10359,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) ARCH(5TE); } else if ((insn & 0x0f000010) == 0x0e000010) { /* Additional coprocessor register transfer. */ - } else if ((insn & 0x0ff10020) == 0x01000000) { - uint32_t mask; - uint32_t val; - /* cps (privileged) */ - if (IS_USER(s)) - return; - mask = val = 0; - if (insn & (1 << 19)) { - if (insn & (1 << 8)) - mask |= CPSR_A; - if (insn & (1 << 7)) - mask |= CPSR_I; - if (insn & (1 << 6)) - mask |= CPSR_F; - if (insn & (1 << 18)) - val |= mask; - } - if (insn & (1 << 17)) { - mask |= CPSR_M; - val |= (insn & 0x1f); - } - if (mask) { - gen_set_psr_im(s, mask, 0, val); - } - return; } goto illegal_op; } @@ -10454,7 +10467,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 addr; @@ -10730,31 +10742,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0: /* msr cpsr, in decodetree */ case 1: /* msr spsr, in decodetree */ goto illegal_op; - case 2: /* cps, nop-hint. */ - /* nop hints in decodetree */ - /* Implemented as NOP in user mode. */ - if (IS_USER(s)) - break; - offset = 0; - imm = 0; - if (insn & (1 << 10)) { - if (insn & (1 << 7)) - offset |= CPSR_A; - if (insn & (1 << 6)) - offset |= CPSR_I; - if (insn & (1 << 5)) - offset |= CPSR_F; - if (insn & (1 << 9)) - imm = CPSR_A | CPSR_I | CPSR_F; - } - if (insn & (1 << 8)) { - offset |= 0x1f; - imm |= (insn & 0x1f); - } - if (offset) { - gen_set_psr_im(s, offset, 0, imm); - } - break; + case 2: /* cps, nop-hint, in decodetree */ + goto illegal_op; case 3: /* Special control operations, in decodetree */ case 4: /* bxj, in decodetree */ goto illegal_op; diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index c7e9df8030..de611e8aff 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -35,9 +35,12 @@ BLX_i 1111 101 . ........................ &i imm=%imm24h &rfe rn w pu &srs mode w pu +&cps mode imod M A I F RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe SRS 1111 100 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs +CPS 1111 0001 0000 imod:2 M:1 0 0000 000 A:1 I:1 F:1 0 mode:5 \ + &cps # Clear-Exclusive, Barriers diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 63bca82575..11a9a2ef58 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -44,6 +44,7 @@ &bfi !extern rd rn lsb msb &sat !extern rd rn satimm imm sh &pkh !extern rd rn rm imm tb +&cps !extern mode imod M A I F # Data-processing (register) @@ -306,6 +307,10 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm NOP 1111 0011 1010 1111 1000 0000 ---- ---- } + # If imod == '00' && M == '0' then SEE "Hint instructions", above. + CPS 1111 0011 1010 1111 1000 0 imod:2 M:1 A:1 I:1 F:1 mode:5 \ + &cps + # Miscellaneous control { CLREX 1111 0011 1011 1111 1000 1111 0010 1111