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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:20 -0700 Message-Id: <20190904193059.26202-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v4 30/69] target/arm: Diagnose too few registers in list for LDM/STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This has been a TODO item for quite a while. The minimum bit count for A32 and T16 is 1, and for T32 is 2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index b67e7389d3..b623dbcd48 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9846,7 +9846,7 @@ static void op_addr_block_post(DisasContext *s, arg_ldst_block *a, } } -static bool op_stm(DisasContext *s, arg_ldst_block *a) +static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool user = a->u; @@ -9863,7 +9863,10 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a) list = a->list; n = ctpop16(list); - /* TODO: test invalid n == 0 case */ + if (n < min_n) { + unallocated_encoding(s); + return true; + } addr = op_addr_block_pre(s, a, n); mem_idx = get_mem_index(s); @@ -9896,7 +9899,8 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a) static bool trans_STM(DisasContext *s, arg_ldst_block *a) { - return op_stm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return op_stm(s, a, 1); } static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) @@ -9906,10 +9910,11 @@ static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) unallocated_encoding(s); return true; } - return op_stm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return op_stm(s, a, 2); } -static bool do_ldm(DisasContext *s, arg_ldst_block *a) +static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool loaded_base; @@ -9938,7 +9943,10 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a) list = a->list; n = ctpop16(list); - /* TODO: test invalid n == 0 case */ + if (n < min_n) { + unallocated_encoding(s); + return true; + } addr = op_addr_block_pre(s, a, n); mem_idx = get_mem_index(s); @@ -10006,7 +10014,8 @@ static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) unallocated_encoding(s); return true; } - return do_ldm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return do_ldm(s, a, 1); } static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) @@ -10016,7 +10025,8 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) unallocated_encoding(s); return true; } - return do_ldm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return do_ldm(s, a, 2); } /*