From patchwork Wed Sep 4 19:30:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 172981 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp366712ilq; Wed, 4 Sep 2019 12:50:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqzwo8G3JG7EkFP9iEXaKIpB04+ynz1DiLzZG1NogKAJQUfyFP56vZ33jLzevX0f2LCXC19H X-Received: by 2002:a37:9303:: with SMTP id v3mr42354351qkd.369.1567626605680; Wed, 04 Sep 2019 12:50:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567626605; cv=none; d=google.com; s=arc-20160816; b=KR07u6dXjDN75Z6PHIuQG6pcm0vEINsxXqLZoGsayvsaZrfizu4GuKxhuRYpzYIEKO ume5XtIGpjs2bA3/pS7iHQawStMq0hhVF8XvoqegRSxrrUFV0BYObmeUnmRwR3o8sZLQ NF7I4GTSRAR4yQ8n26+s1gQeQJUrwd4z9RkEpYMc8UykZQnlsgaQJxSpJpEMz86+hMbS 4mXLa10H/MP4KeKC72mVWYXSm9mK7LDvnESk1cWCbRYotN5Nd/M/fdVFnDtkzc92XCE0 FTBZcBvFD8JGbXHnisTjhr8d376bjMiE52DlCqLoG6WUqW+aovLnVErh8Lk03352QNVA 8aQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=p0cMte2SRC3KsDP3LAvH1k1gjZ4hGiRJKgyQQsOuHnA=; b=g8N1QDEvsZBOg7t1WEU7Hcrz1NEfdJ5OC23Kyec2rtTiC5Jb6RhgXjrDRPr2WZuSiI rURlFcWNuK+NILpKndRaAxi0y3q60+cJE2DJOT3PGqZE9Kj6PqzGHPRflHqkLgj1i+qJ qc3dMbDReAdsJ+T23C+PeCo6OXWrjlpnojrOFp7D78yao7kgLQ9AVGeedKPMBnLuLWcI 2ed2dBxpRPaK2XOPWrwu7tmEaoxzib2twZwCm5mfhSxTACcvG8vO26XAgJCcDYRVWadR 3DaJJkyguTrRfEqF1J5waJ/GXPoR+2VyCliNuwq+KeHOj+itx/LBLwS1RVwjDvKM9dxo se1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ld91WBGk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f7si7319650qvd.66.2019.09.04.12.50.05 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 04 Sep 2019 12:50:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ld91WBGk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37860 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bI4-0006TT-5x for patch@linaro.org; Wed, 04 Sep 2019 15:50:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40020) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5azy-0004Ni-0t for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5azw-0002H5-2b for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:21 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:36127) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5azv-0002GF-QF for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:19 -0400 Received: by mail-pl1-x641.google.com with SMTP id f19so6951plr.3 for ; Wed, 04 Sep 2019 12:31:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=p0cMte2SRC3KsDP3LAvH1k1gjZ4hGiRJKgyQQsOuHnA=; b=ld91WBGkyc8h/T2O9bfWaE+zmvsMDDewA2X5eV/oEOMTosAU3Uz9mIHepKWN/7q3Ld xxNIg32lhZ2unF63sEytbzpNblpnRB5iCmWRkGGaNYuSQlqvepU0prO0NtJgSN3d1Hd0 Ph+Vp0hOvFXZsIJzhTDZj09/h5wYpvTB/jKvImVAsCuYieRjKsqUkq3UxhaTTCZyJRxp 3Vu8Dj7aDWWgqhDVs8XKzvt62t2MZOch2zC7SvZgSbQf8Tf2euKupVXvJT4cODSqg3xQ I7JZTgRsDqmeDVYwrOZSxlFPIOZkfSlzxPz5Bt7VBACSP9PvxfcuGu1QEweZsDTVn1pC Vcbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=p0cMte2SRC3KsDP3LAvH1k1gjZ4hGiRJKgyQQsOuHnA=; b=RuNPxrDm6K3L/80BIZ3z6OiVpPV/Ly/unyjkd6Iy8V1o8sxbZw//r305Kx2aNTZLwL SQxm5lyKTp4aqry0P5L6hKSs1S4mDUcYbI9zNBq1tdaone7q1ZVhgqpuec/CNYlK6oBI OPWE2qVm4H0Ynr2939YJAih0c6V/8fCtS8WWfxjC3LPjbxS2eYkEbQ5RuUYTVdXseY8k d7jiSJpZJP9bjgaBz39ec/VOcm9FhBN3H8JApVTF9geslRG2gK3zXYaAJZnxEZm2DzCR HmQ9Iihy3ZO+p6It7W8X8BHMQBgWVeqdWgl9lWWRAB+IP9S05ubFsdZukIx6sfbCYjMe BCZQ== X-Gm-Message-State: APjAAAWN8Tx+c4KaW4NW7cAZ28Vm8QAxaP95He48bb81ts30l9n8EF3r WvvND3pzG1wOMLhyijbFOYenSxcqayk= X-Received: by 2002:a17:902:8202:: with SMTP id x2mr3071331pln.182.1567625478468; Wed, 04 Sep 2019 12:31:18 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:04 -0700 Message-Id: <20190904193059.26202-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v4 14/69] target/arm: Convert Cyclic Redundancy Check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 121 +++++++++++++++++++---------------------- target/arm/a32.decode | 9 +++ target/arm/t32.decode | 7 +++ 3 files changed, 72 insertions(+), 65 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 02dd4a2ab8..9d3f31f569 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8320,6 +8320,57 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) return true; } +/* + * Cyclic Redundancy Check + */ + +static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, MemOp sz) +{ + TCGv_i32 t1, t2, t3; + + if (!dc_isar_feature(aa32_crc32, s)) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + switch (sz) { + case MO_8: + gen_uxtb(t2); + break; + case MO_16: + gen_uxth(t2); + break; + case MO_32: + break; + default: + g_assert_not_reached(); + } + t3 = tcg_const_i32(1 << sz); + if (c) { + gen_helper_crc32c(t1, t1, t2, t3); + } else { + gen_helper_crc32(t1, t1, t2, t3); + } + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + store_reg(s, a->rd, t1); + return true; +} + +#define DO_CRC32(NAME, c, sz) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ + { return op_crc32(s, a, c, sz); } + +DO_CRC32(CRC32B, false, MO_8) +DO_CRC32(CRC32H, false, MO_16) +DO_CRC32(CRC32W, false, MO_32) +DO_CRC32(CRC32CB, true, MO_8) +DO_CRC32(CRC32CH, true, MO_16) +DO_CRC32(CRC32CW, true, MO_32) + +#undef DO_CRC32 + /* * Miscellaneous instructions */ @@ -8735,39 +8786,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) gen_bx(s, tmp); break; case 0x4: - { - /* crc32/crc32c */ - uint32_t c = extract32(insn, 8, 4); - - /* Check this CPU supports ARMv8 CRC instructions. - * op1 == 3 is UNPREDICTABLE but handle as UNDEFINED. - * Bits 8, 10 and 11 should be zero. - */ - if (!dc_isar_feature(aa32_crc32, s) || op1 == 0x3 || (c & 0xd) != 0) { - goto illegal_op; - } - - rn = extract32(insn, 16, 4); - rd = extract32(insn, 12, 4); - - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if (op1 == 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (op1 == 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 = tcg_const_i32(1 << op1); - if (c & 0x2) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - store_reg(s, rd, tmp); - break; - } + /* crc32 */ + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; case 0x5: /* Saturating addition and subtraction. */ /* All done in decodetree. Reach here for illegal ops. */ @@ -10216,16 +10237,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } break; - case 0x20: /* crc32/crc32c */ + case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: case 0x28: case 0x29: case 0x2a: - if (!dc_isar_feature(aa32_crc32, s)) { - goto illegal_op; - } - break; + goto illegal_op; default: goto illegal_op; } @@ -10254,33 +10272,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0x18: /* clz */ tcg_gen_clzi_i32(tmp, tmp, 32); break; - case 0x20: - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - { - /* crc32/crc32c */ - uint32_t sz = op & 0x3; - uint32_t c = op & 0x8; - - tmp2 = load_reg(s, rm); - if (sz == 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (sz == 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 = tcg_const_i32(1 << sz); - if (c) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - break; - } default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 6ee12c1140..a8ef435b15 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -182,6 +182,15 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1 +# Cyclic Redundancy Check + +CRC32B .... 0001 0000 .... .... 0000 0100 .... @rndm +CRC32H .... 0001 0010 .... .... 0000 0100 .... @rndm +CRC32W .... 0001 0100 .... .... 0000 0100 .... @rndm +CRC32CB .... 0001 0000 .... .... 0010 0100 .... @rndm +CRC32CH .... 0001 0010 .... .... 0010 0100 .... @rndm +CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm + # Miscellaneous instructions %sysm 8:1 16:4 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 98b682e7ec..261db100ff 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -172,6 +172,13 @@ QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm +CRC32B 1111 1010 1100 .... 1111 .... 1000 .... @rndm +CRC32H 1111 1010 1100 .... 1111 .... 1001 .... @rndm +CRC32W 1111 1010 1100 .... 1111 .... 1010 .... @rndm +CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm +CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm +CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm + # Branches and miscellaneous control %msr_sysm 4:1 8:4