[25/36] cputlb: Remove double-alignment in store_helper

Message ID	20190903160858.5296-26-richard.henderson@linaro.org
State	Accepted
Commit	5787585d0406cfd54dda0c71ea1a603347ce6e71
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Tue, 3 Sep 2019 09:08:47 -0700 Message-Id: <20190903160858.5296-26-richard.henderson@linaro.org> In-Reply-To: <20190903160858.5296-1-richard.henderson@linaro.org> References: <20190903160858.5296-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH 25/36] cputlb: Remove double-alignment in store_helper Precedence: list Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg patch queue \| expand [00/36] tcg patch queue [01/36] tcg: TCGMemOp is now accelerator independent MemOp [02/36] memory: Introduce size_memop [03/36] target/mips: Access MemoryRegion with MemOp [04/36] hw/s390x: Access MemoryRegion with MemOp [05/36] hw/intc/armv7m_nic: Access MemoryRegion with MemOp [06/36] hw/virtio: Access MemoryRegion with MemOp [07/36] hw/vfio: Access MemoryRegion with MemOp [08/36] exec: Access MemoryRegion with MemOp [09/36] cputlb: Access MemoryRegion with MemOp [10/36] memory: Access MemoryRegion with MemOp [11/36] hw/s390x: Hard code size with MO_{8\|16\|32\|64} [12/36] target/mips: Hard code size with MO_{8\|16\|32\|64} [13/36] exec: Hard code size with MO_{8\|16\|32\|64} [14/36] memory: Access MemoryRegion with endianness [15/36] cputlb: Replace size and endian operands for MemOp [16/36] memory: Single byte swap along the I/O path [17/36] cputlb: Byte swap memory transaction attribute [18/36] target/sparc: Add TLB entry with attributes [19/36] target/sparc: sun4u Invert Endian TTE bit [20/36] exec: Move user-only watchpoint stubs inline [21/36] exec: Factor out core logic of check_watchpoint() [22/36] cputlb: Fold TLB_RECHECK into TLB_INVALID_MASK [23/36] exec: Factor out cpu_watchpoint_address_matches [24/36] cputlb: Fix size operand for tlb_fill on unaligned store [25/36] cputlb: Remove double-alignment in store_helper [26/36] cputlb: Handle watchpoints via TLB_WATCHPOINT [27/36] tcg: Check for watchpoints in probe_write() [28/36] s390x/tcg: Use guest_addr_valid() instead of h2g_valid() in probe_write_access() [29/36] s390x/tcg: Fix length calculation in probe_write_access() [30/36] tcg: Factor out CONFIG_USER_ONLY probe_write() from s390x code [31/36] tcg: Enforce single page access in probe_write() [32/36] mips/tcg: Call probe_write() for CONFIG_USER_ONLY as well [33/36] hppa/tcg: Call probe_write() also for CONFIG_USER_ONLY [34/36] s390x/tcg: Pass a size to probe_write() in do_csst() [35/36] tcg: Make probe_write() return a pointer to the host page [36/36] tcg: Factor out probe_write() logic into probe_access()

Message ID

20190903160858.5296-26-richard.henderson@linaro.org

State

Accepted

Commit

5787585d0406cfd54dda0c71ea1a603347ce6e71

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Tue,  3 Sep 2019 09:08:47 -0700
Message-Id: <20190903160858.5296-26-richard.henderson@linaro.org>
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Subject: [Qemu-devel] [PATCH 25/36] cputlb: Remove double-alignment in
	store_helper
Precedence: list
Cc: peter.maydell@linaro.org
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Series

tcg patch queue | expand

Commit Message

Richard Henderson Sept. 3, 2019, 4:08 p.m. UTC

We have already aligned page2 to the start of the next page.
There is no reason to do that a second time.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Reviewed-by: David Hildenbrand <david@redhat.com>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 accel/tcg/cputlb.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

-- 
2.17.1

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 7fb67d2f05..d0f8db33a2 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1518,8 +1518,7 @@  store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
         entry2 = tlb_entry(env, mmu_idx, page2);
         tlb_addr2 = tlb_addr_write(entry2);
         if (!tlb_hit_page(tlb_addr2, page2)
-            && !victim_tlb_hit(env, mmu_idx, index2, tlb_off,
-                               page2 & TARGET_PAGE_MASK)) {
+            && !victim_tlb_hit(env, mmu_idx, index2, tlb_off, page2)) {
             tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE,
                      mmu_idx, retaddr);
         }

[25/36] cputlb: Remove double-alignment in store_helper

Commit Message

Patch