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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:36:54 -0700 Message-Id: <20190819213755.26175-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 07/68] target/arm: Simplify UMAAL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_mulu2_i32 and tcg_gen_add2_i32. Signed-off-by: Richard Henderson --- target/arm/translate.c | 34 ++++++++++++---------------------- 1 file changed, 12 insertions(+), 22 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 94659086c0..82bd207799 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7324,21 +7324,6 @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val) store_reg(s, rhigh, tmp); } -/* load a 32-bit value from a register and perform a 64-bit accumulate. */ -static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow) -{ - TCGv_i64 tmp; - TCGv_i32 tmp2; - - /* Load value and extend to 64 bits. */ - tmp = tcg_temp_new_i64(); - tmp2 = load_reg(s, rlow); - tcg_gen_extu_i32_i64(tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_gen_add_i64(val, val, tmp); - tcg_temp_free_i64(tmp); -} - /* load and add a 64-bit value from a register pair. */ static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) { @@ -8090,8 +8075,7 @@ static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) { - TCGv_i32 t0, t1; - TCGv_i64 t64; + TCGv_i32 t0, t1, t2, zero; if (s->thumb ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) @@ -8101,11 +8085,17 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) t0 = load_reg(s, a->rm); t1 = load_reg(s, a->rn); - t64 = gen_mulu_i64_i32(t0, t1); - gen_addq_lo(s, t64, a->ra); - gen_addq_lo(s, t64, a->rd); - gen_storeq_reg(s, a->ra, a->rd, t64); - tcg_temp_free_i64(t64); + tcg_gen_mulu2_i32(t0, t1, t0, t1); + zero = tcg_const_i32(0); + t2 = load_reg(s, a->ra); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + t2 = load_reg(s, a->rd); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(zero); + store_reg(s, a->ra, t0); + store_reg(s, a->rd, t1); return true; }