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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:16 -0700 Message-Id: <20190819213755.26175-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v2 29/68] target/arm: Diagnose too few registers in list for LDM/STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This has been a TODO item for quite a while. The minimum bit count for A32 and T16 is 1, and for T32 is 2. Signed-off-by: Richard Henderson --- target/arm/translate.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 29e2eae441..1792bb7abd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9733,7 +9733,7 @@ static void op_addr_block_post(DisasContext *s, arg_ldst_block *a, } } -static bool op_stm(DisasContext *s, arg_ldst_block *a) +static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool user = a->u; @@ -9749,7 +9749,9 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a) list = a->list; n = ctpop16(list); - /* TODO: test invalid n == 0 case */ + if (n < min_n) { + return false; + } addr = op_addr_block_pre(s, a, n); mem_idx = get_mem_index(s); @@ -9782,7 +9784,8 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a) static bool trans_STM(DisasContext *s, arg_ldst_block *a) { - return op_stm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return op_stm(s, a, 1); } static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) @@ -9791,10 +9794,11 @@ static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) if (a->w && (a->list & (1 << a->rn))) { return false; } - return op_stm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return op_stm(s, a, 2); } -static bool do_ldm(DisasContext *s, arg_ldst_block *a) +static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool loaded_base; @@ -9821,7 +9825,9 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a) list = a->list; n = ctpop16(list); - /* TODO: test invalid n == 0 case */ + if (n < min_n) { + return false; + } addr = op_addr_block_pre(s, a, n); mem_idx = get_mem_index(s); @@ -9888,7 +9894,8 @@ static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) if (ENABLE_ARCH_7 && a->w && (a->list & (1 << a->rn))) { return false; } - return do_ldm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return do_ldm(s, a, 1); } static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) @@ -9897,7 +9904,8 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) if (a->w && (a->list & (1 << a->rn))) { return false; } - return do_ldm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return do_ldm(s, a, 2); } /*