From patchwork Mon Aug 19 21:37:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171676 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3539212ily; Mon, 19 Aug 2019 14:51:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqw42Y8sTZXx5KRflPCAw/WcQ8BneCg9IGfZQVnQ/M68uwWSIQrm2qa85ui0qvgY2RhooiJ5 X-Received: by 2002:a50:ce5a:: with SMTP id k26mr27653134edj.218.1566251511189; Mon, 19 Aug 2019 14:51:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251511; cv=none; d=google.com; s=arc-20160816; b=0+3auU45Iu+Ltpw8ArjJ0ac3mDs4lTP5hyGKWU4cTJ8xaIp+zOkJt5nwoSo+oatpFD 3RKcTw4MfQCrws+WpllJ3u4MqJEm1VSDv32xJqbMEjXdaaeeSnp/ypBm8CpbyCh54bkC R37T/rTghaX94tb+gePszX/NkXM6Qb0hWM6C3rk42jMDhb8ogA4CWy1qUIRcYgAu8r0d kWXGU7KNuxdDMVG8qPVtn8wdjYhR1uOxjRXcQerLGmH89Jz0irpP9grElUZnIB1ZkFU9 FXbV/DgoAgrcqN5xmNI3OMM5PumI76db8/QSbneM1H6WCgAxy9f3NI1u+cFAxtcPjQFn v27g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=meGInlCcNAs08b5g91xBiKJHgrSzZAc6MsZg23QrFBY=; b=qMPugCzN+WEbxQpV72VnnubZSDgjNtBz9wUlEQNh4zCuOScrlpGtiawC5VkvbYtKqd ednx4utj1zC8qxDOQcFEZrifIU4PCS6YTwnOS1JteYnxcdyxnHl6f0f3U9ObzlE2qA12 rfxJ4HoZ5P/rrNVeiMaQsQ234wyIoEZNy8C+LR+pFFzO9FdTOFPfdMUL+Pe7pRYpuG52 EUC2S7JQ3ScdIZs0zR1bCcGfyoD6RdxctEdGp8mJyGNGde6XCyFIhegRYpNZMer7K5fY ZRgzx5hixOc1e7OqXDb5P2gRb5XhM2KRjRl7yhtbz9MqvS2uxxzVPrSemSXcM/uJQiUa VJzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cGOujrt0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k17si5269500ejd.222.2019.08.19.14.51.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Aug 2019 14:51:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cGOujrt0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59144 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpZ7-00015b-BC for patch@linaro.org; Mon, 19 Aug 2019 17:51:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58892) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpM7-0001it-3U for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpM5-0006Bc-Mf for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:22 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:43895) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpM5-0006B5-Fd for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:21 -0400 Received: by mail-pl1-x644.google.com with SMTP id 4so1583889pld.10 for ; Mon, 19 Aug 2019 14:38:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=meGInlCcNAs08b5g91xBiKJHgrSzZAc6MsZg23QrFBY=; b=cGOujrt0tiWOvMliBVmVSwC+8Hpw+CNrSgRshPtDFImmTj84oz1ZBmoqDzOBzMjtc2 o6rSnAxOw9xLn3bfeZJZm+857Q9SIE86aUVjxKw/VuVx2lXbDhLQJHDiat3eKWxOqROx g80Csa6aGzZVwTfEA0eMQjfdk2KqpmCzzHXWTOEw5WSXuI3jq++t0WfKzabQNVClk0Wx ntckX+nodPby1IpKAh7M5hVnv8AXCiPV35lfopqf4dcUHyOjJClw7XMIgdkBD1044J8P 1HcZEwO7exniz1u05OtoBRRyGWNnHi43zYPmacV74vYSCq7qMd4hlniADipZuNscf+jj M8eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=meGInlCcNAs08b5g91xBiKJHgrSzZAc6MsZg23QrFBY=; b=EjydBoa9XAnR8ntqs+zlaKMyn2FutarQFCInD6XkPRO0iIkoNpwUvN12cjdWxyVgWG EydCpWD/TtyOJVnPR+mIbPM0dV47WW/AUdjo6x1muF33UmjatBSgwckSvM+NgjQqpWmr umyuN9vnXSKr0g/KiKN9VWRfNJUlF3/oncGWp/Aw7EVBrTXHxnhJ78VNb2BlBkpfQoEt EJ4VXUtf5d5fwAnk79SehtREC7B6ZfLPGEXrzcUwJGFU2Ug5dkUEJBegktBGG3g9vn+7 ARQC+UyqGLO5AdDP3ElXtpUgUUzEIJon8cNwb94Rsq6cmYniIkClhdvXfMyQVKhlnc3Y Ku1g== X-Gm-Message-State: APjAAAU1jjgcThOPcRogsWrvD8fnEpAl5HDQ/fbDAxQgD+Kexb/Wj5sY BSJ79SvvFfwMJG9W7MIiW1qZboI3620= X-Received: by 2002:a17:902:834c:: with SMTP id z12mr10863794pln.8.1566250700118; Mon, 19 Aug 2019 14:38:20 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:05 -0700 Message-Id: <20190819213755.26175-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 18/68] target/arm: Convert the rest of A32 Miscelaneous instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This fixes an exiting bug with the T5 encoding of SUBS PC, LR, #IMM, in that it may be executed from user mode as with any other encoding of SUBS, not as ERET. Signed-off-by: Richard Henderson --- target/arm/translate.c | 119 +++++++++++++---------------------------- target/arm/a32.decode | 8 +++ target/arm/t32.decode | 5 ++ 3 files changed, 50 insertions(+), 82 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index cb7b35489f..cb6296dc12 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8491,6 +8491,39 @@ static bool trans_ERET(DisasContext *s, arg_ERET *a) return true; } +static bool trans_HLT(DisasContext *s, arg_HLT *a) +{ + gen_hlt(s, a->imm); + return true; +} + +static bool trans_BKPT(DisasContext *s, arg_BKPT *a) +{ + if (!ENABLE_ARCH_5) { + return false; + } + gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); + return true; +} + +static bool trans_HVC(DisasContext *s, arg_HVC *a) +{ + if (!ENABLE_ARCH_7 || IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_hvc(s, a->imm); + return true; +} + +static bool trans_SMC(DisasContext *s, arg_SMC *a) +{ + if (!ENABLE_ARCH_6K || IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_smc(s); + return true; +} + /* * Legacy decoder. */ @@ -8771,68 +8804,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } else if ((insn & 0x0f900000) == 0x01000000 && (insn & 0x00000090) != 0x00000090) { /* miscellaneous instructions */ - op1 = (insn >> 21) & 3; - sh = (insn >> 4) & 0xf; - rm = insn & 0xf; - switch (sh) { - case 0x0: - /* MSR/MRS (banked/register) */ - /* All done in decodetree. Illegal ops already signalled. */ - g_assert_not_reached(); - case 0x1: /* bx, clz */ - case 0x2: /* bxj */ - case 0x3: /* blx */ - case 0x4: /* crc32 */ - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - case 0x5: /* Saturating addition and subtraction. */ - case 0x6: /* ERET */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - case 7: - { - int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4); - switch (op1) { - case 0: - /* HLT */ - gen_hlt(s, imm16); - break; - case 1: - /* bkpt */ - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false)); - break; - case 2: - /* Hypervisor call (v7) */ - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - break; - case 3: - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - break; - default: - g_assert_not_reached(); - } - break; - } - case 0x8: - case 0xa: - case 0xc: - case 0xe: - /* Halfword multiply and multiply accumulate. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - default: - goto illegal_op; - } + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; } else if (((insn & 0x0e000000) == 0 && (insn & 0x00000090) != 0x90) || ((insn & 0x0e000000) == (1 << 25))) { @@ -10493,26 +10466,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; if (insn & (1 << 26)) { - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - if (!(insn & (1 << 20))) { - /* Hypervisor call (v7) */ - int imm16 = extract32(insn, 16, 4) << 12 - | extract32(insn, 0, 12); - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - } else { - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - } + /* hvc, smc, in decodetree */ + goto illegal_op; } else { op = (insn >> 20) & 7; switch (op) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 52a66dd1d5..c7f156be6d 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -31,6 +31,7 @@ &rrr rd rn rm &rr rd rm &r rm +&i imm &msr_reg rn r mask &mrs_reg rd r &msr_bank rn r sysm @@ -196,9 +197,11 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm # Miscellaneous instructions %sysm 8:1 16:4 +%imm16_8_0 8:12 0:4 @rm ---- .... .... .... .... .... .... rm:4 &r @rdm ---- .... .... .... rd:4 .... .... rm:4 &rr +@i16 ---- .... .... .... .... .... .... .... &i imm=%imm16_8_0 MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm @@ -213,3 +216,8 @@ BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm ERET ---- 0001 0110 0000 0000 0000 0110 1110 + +HLT .... 0001 0000 .... .... .... 0111 .... @i16 +BKPT .... 0001 0010 .... .... .... 0111 .... @i16 +HVC .... 0001 0100 .... .... .... 0111 .... @i16 +SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 6236d28b99..5116c6165a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -28,6 +28,7 @@ &rrr !extern rd rn rm &rr !extern rd rm &r !extern rm +&i !extern imm &msr_reg !extern rn r mask &mrs_reg !extern rd r &msr_bank !extern rn r sysm @@ -189,6 +190,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm %msr_sysm 4:1 8:4 %mrs_sysm 4:1 16:4 +%imm16_16_0 16:4 0:12 { { @@ -226,4 +228,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ &s_rri_rot rot=0 s=1 rd=15 rn=14 } + SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i + HVC 1111 0111 1110 .... 1000 .... .... .... \ + &i imm=%imm16_16_0 }