From patchwork Mon Aug 19 21:37:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 171672 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp3537460ily; Mon, 19 Aug 2019 14:49:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqwvPvRnfSsvW5qrIcAMg8e4OmM/arQRGxq6AGbpJA1SpJ0iubX/CklMu9VR0eqNLKlM8OzI X-Received: by 2002:a50:f746:: with SMTP id j6mr21552655edn.51.1566251374489; Mon, 19 Aug 2019 14:49:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566251374; cv=none; d=google.com; s=arc-20160816; b=m8vLn9MvjGIH/VMxfYol/o/4QvphrIb8VEnF3tktj4E6CuLnxGxcC0rHIp5rTdxuDQ pPfjVe118eO8p82EOfsct4gbNZHNGkRnPFIT5pu9cdRf4+TvQwfEs+EOWwb4y3prm7ml Z5inrIoC8YIz71x2zRf+1jk5nahvM07hpeqFsPlQ+VD8zpRBBWnMRzFa+8DfgimtWwnZ kL45nLA34fzs2kXypX4a4eJq9HVpT/aYkDOgs1kOAiVbFEHwCbE/DA4FUTTHiDyiEdck Z4xsIoACEzKsHZsaqV2AAUEH8g55Ps6PWkC5xs+26k4VuPWUB/7UkH7tllZuomyQkeuX kiKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=7Eta9ZtvQ0oDIOcJ2OoQMP0oMhVWN+OV+wP28xTcUIs=; b=AYhbyXD9Bc6RmaDmtCOPbe5rI0n70zIcGONxtLuGQajZYJ5jEadYtNMeGTkvv9Ldex Nn/wOE/m39hRxo/PQbm85CJn7YtY54JcZZmp5WlIZRYB+Y1KyvBzESYcH/AwcSnTngIk 4xV23DaZNF8159bGkdXg0ny3fh8LbjVgSzic3RNZOsuaiJjJeag30jbmQiCArGsejner /Q1ZGRv9puKgZ+Qi39n2iUdchFRjmRS5QmMTKMotylmutrk35hkZjqVJLHhqM3CXpBoc N4u6tozxkuDRzh9pm0JXALtGj/J6IkdWXSKKOZq/zxSxv+TR50Mks/3CeRBH9tB+OpZ1 VnvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CeL1dswG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z7si9506504edb.55.2019.08.19.14.49.34 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 19 Aug 2019 14:49:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CeL1dswG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59088 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpWu-0005mT-Tm for patch@linaro.org; Mon, 19 Aug 2019 17:49:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58783) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1hzpM2-0001a4-1H for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hzpM0-00068L-BI for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:17 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:44256) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hzpM0-00067w-5M for qemu-devel@nongnu.org; Mon, 19 Aug 2019 17:38:16 -0400 Received: by mail-pl1-x643.google.com with SMTP id t14so1574231plr.11 for ; Mon, 19 Aug 2019 14:38:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7Eta9ZtvQ0oDIOcJ2OoQMP0oMhVWN+OV+wP28xTcUIs=; b=CeL1dswG3Eb8rIKISt5NQW8orqLZrsq8get5MJ1vBFHRznDsbE3PMt2rD5USdxcw0A GHiI76ST3VdwGXxJGGDAe2w5X4/UJPSQzaT1yXTlpCPepOJB04d5BDFSGVFB7oSdDr4T NFVhiDaVWwgBWUM3lucSv/hzAUCtwbdDyVjWQ3Y9B6ytwVORLcG+Evkp1lFd0o+Kau6t FHK4E5Ih0nEdMnRD3I4DLXZ42OvwSi3q0Iq4ek2gOcAlm2LoNkbYoPHkJWbxur2qWkmK 5YHjnTy13kryH+ieXt6SPJPM1zwLRM5ckxYm/H0T+vPXq0x3bYDU/bCRatL3CaiD71UY MhpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7Eta9ZtvQ0oDIOcJ2OoQMP0oMhVWN+OV+wP28xTcUIs=; b=V1wZgn36AKK5wH03OMgXsSWk1z0G+fY+ki3GoFaHdQ9ZKnGbFaM8yJhkFEbMZ4uzdE OhZSdufc1TKfDQlrBxG4wXxW2JxrjA3FaPMcWJsKNddblS0njZVl3/N6sFQ3iNd5ay3C j3HnaRxwKnajSd/PE00rUBIkWnOsG+nMLBqcM/lIE+9x7O1qptezF2NDP7fkbYlv/YEh dg5B4INjR2Xr8BD9sYrGLyX03mCii2imG/LTQUhNIUwSno+lCbIJ1hTCJrwK6V4Mawth a0+jVVuC6rcVagO8WapQuGtohfwpeDjshwrDnbXTmRBPyeV2L/dANjTG7rdzWc01QP51 WYRg== X-Gm-Message-State: APjAAAVfnjXbl1WivbvV1yj5aRjsySqWt0yhPQo93TPmePC59cQa5Ex0 le0i8yXOVYtXdYD3L+++zNjwJ2GEcL8= X-Received: by 2002:a17:902:5a1:: with SMTP id f30mr25193212plf.64.1566250694884; Mon, 19 Aug 2019 14:38:14 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id d2sm13446951pjs.21.2019.08.19.14.38.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Aug 2019 14:38:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 19 Aug 2019 14:37:01 -0700 Message-Id: <20190819213755.26175-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org> References: <20190819213755.26175-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 14/68] target/arm: Convert Cyclic Redundancy Check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 121 +++++++++++++++++++---------------------- target/arm/a32.decode | 9 +++ target/arm/t32.decode | 7 +++ 3 files changed, 72 insertions(+), 65 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 026abcaa9c..f390656ce9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8291,6 +8291,57 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) return true; } +/* + * Cyclic Redundancy Check + */ + +static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, TCGMemOp sz) +{ + TCGv_i32 t1, t2, t3; + + if (!dc_isar_feature(aa32_crc32, s)) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + switch (sz) { + case MO_8: + gen_uxtb(t2); + break; + case MO_16: + gen_uxth(t2); + break; + case MO_32: + break; + default: + g_assert_not_reached(); + } + t3 = tcg_const_i32(1 << sz); + if (c) { + gen_helper_crc32c(t1, t1, t2, t3); + } else { + gen_helper_crc32(t1, t1, t2, t3); + } + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + store_reg(s, a->rd, t1); + return true; +} + +#define DO_CRC32(NAME, c, sz) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ + { return op_crc32(s, a, c, sz); } + +DO_CRC32(CRC32B, false, MO_8) +DO_CRC32(CRC32H, false, MO_16) +DO_CRC32(CRC32W, false, MO_32) +DO_CRC32(CRC32CB, true, MO_8) +DO_CRC32(CRC32CH, true, MO_16) +DO_CRC32(CRC32CW, true, MO_32) + +#undef DO_CRC32 + /* * Miscellaneous instructions */ @@ -8706,39 +8757,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) gen_bx(s, tmp); break; case 0x4: - { - /* crc32/crc32c */ - uint32_t c = extract32(insn, 8, 4); - - /* Check this CPU supports ARMv8 CRC instructions. - * op1 == 3 is UNPREDICTABLE but handle as UNDEFINED. - * Bits 8, 10 and 11 should be zero. - */ - if (!dc_isar_feature(aa32_crc32, s) || op1 == 0x3 || (c & 0xd) != 0) { - goto illegal_op; - } - - rn = extract32(insn, 16, 4); - rd = extract32(insn, 12, 4); - - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if (op1 == 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (op1 == 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 = tcg_const_i32(1 << op1); - if (c & 0x2) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - store_reg(s, rd, tmp); - break; - } + /* crc32 */ + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; case 0x5: /* Saturating addition and subtraction. */ /* All done in decodetree. Reach here for illegal ops. */ @@ -10181,16 +10202,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } break; - case 0x20: /* crc32/crc32c */ + case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: case 0x28: case 0x29: case 0x2a: - if (!dc_isar_feature(aa32_crc32, s)) { - goto illegal_op; - } - break; + goto illegal_op; default: goto illegal_op; } @@ -10219,33 +10237,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0x18: /* clz */ tcg_gen_clzi_i32(tmp, tmp, 32); break; - case 0x20: - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - { - /* crc32/crc32c */ - uint32_t sz = op & 0x3; - uint32_t c = op & 0x8; - - tmp2 = load_reg(s, rm); - if (sz == 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (sz == 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 = tcg_const_i32(1 << sz); - if (c) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - break; - } default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 6ee12c1140..a8ef435b15 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -182,6 +182,15 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1 +# Cyclic Redundancy Check + +CRC32B .... 0001 0000 .... .... 0000 0100 .... @rndm +CRC32H .... 0001 0010 .... .... 0000 0100 .... @rndm +CRC32W .... 0001 0100 .... .... 0000 0100 .... @rndm +CRC32CB .... 0001 0000 .... .... 0010 0100 .... @rndm +CRC32CH .... 0001 0010 .... .... 0010 0100 .... @rndm +CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm + # Miscellaneous instructions %sysm 8:1 16:4 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 98b682e7ec..261db100ff 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -172,6 +172,13 @@ QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm +CRC32B 1111 1010 1100 .... 1111 .... 1000 .... @rndm +CRC32H 1111 1010 1100 .... 1111 .... 1001 .... @rndm +CRC32W 1111 1010 1100 .... 1111 .... 1010 .... @rndm +CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm +CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm +CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm + # Branches and miscellaneous control %msr_sysm 4:1 8:4