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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C604D1FF9A; Mon, 19 Aug 2019 13:17:10 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Mon, 19 Aug 2019 13:17:07 +0100 Message-Id: <20190819121709.31597-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190819121709.31597-1-alex.bennee@linaro.org> References: <20190819121709.31597-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 Subject: [Qemu-devel] [PULL 10/12] target/mips: rationalise softfloat includes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , =?utf-8?q?Alex_Benn=C3=A9e?= , Riku Voipio , qemu-devel@nongnu.org, Laurent Vivier , Aleksandar Markovic , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We should avoid including the whole of softfloat headers in cpu.h and explicitly include it only where we will be calling softfloat functions. We can use the -types.h in cpu.h for the few bits that are global. We also move the restore_snan_bit_mode into internal.h and include -helpers.h there. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic -- 2.20.1 diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index 0ba894fa7aa..39915b3fde2 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "elf.h" +#include "internal.h" # ifdef TARGET_ABI_MIPSO32 # define MIPS_SYS(name, args) args, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 21c0615e020..d235117dab3 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -5,7 +5,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" -#include "fpu/softfloat.h" +#include "fpu/softfloat-types.h" #include "mips-defs.h" #define TCG_GUEST_DEFAULT_MO (0) @@ -1195,12 +1195,6 @@ void itc_reconfigure(struct MIPSITUState *tag); /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); -static inline void restore_snan_bit_mode(CPUMIPSState *env) -{ - set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, - &env->active_fpu.fp_status); -} - static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { diff --git a/target/mips/internal.h b/target/mips/internal.h index d5aa5490d3c..ae29b578a47 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -7,6 +7,7 @@ #ifndef MIPS_INTERNAL_H #define MIPS_INTERNAL_H +#include "fpu/softfloat-helpers.h" /* MMU types, the first four entries have the same layout as the CP0C0_MT field. */ @@ -226,6 +227,12 @@ static inline void restore_flush_mode(CPUMIPSState *env) &env->active_fpu.fp_status); } +static inline void restore_snan_bit_mode(CPUMIPSState *env) +{ + set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, + &env->active_fpu.fp_status); +} + static inline void restore_fp_status(CPUMIPSState *env) { restore_rounding_mode(env); diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index a5a86572b4a..f24061e2af7 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -22,6 +22,7 @@ #include "internal.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "fpu/softfloat.h" /* Data format min and max values */ #define DF_BITS(df) (1 << ((df) + 3)) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 9e2e02f8586..f88a3ab9043 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -25,6 +25,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "sysemu/kvm.h" +#include "fpu/softfloat.h" /*****************************************************************************/ /* Exceptions processing helpers */