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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id v12sm2850146pjk.13.2019.08.08.13.26.21 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 08 Aug 2019 13:26:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Aug 2019 13:26:12 -0700 Message-Id: <20190808202616.13782-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190808202616.13782-1-richard.henderson@linaro.org> References: <20190808202616.13782-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 3/7] target/arm: Remove redundant shift tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The immediate shift generator functions already test for, and eliminate, the case of a shift by zero. Signed-off-by: Richard Henderson --- target/arm/translate.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 94170af134..3ddc404b3b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8826,8 +8826,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) shift = (insn >> 10) & 3; /* ??? In many cases it's not necessary to do a rotate, a shift is sufficient. */ - if (shift != 0) - tcg_gen_rotri_i32(tmp, tmp, shift * 8); + tcg_gen_rotri_i32(tmp, tmp, shift * 8); op1 = (insn >> 20) & 7; switch (op1) { case 0: gen_sxtb16(tmp); break; @@ -9904,8 +9903,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) shift = (insn >> 4) & 3; /* ??? In many cases it's not necessary to do a rotate, a shift is sufficient. */ - if (shift != 0) - tcg_gen_rotri_i32(tmp, tmp, shift * 8); + tcg_gen_rotri_i32(tmp, tmp, shift * 8); op = (insn >> 20) & 7; switch (op) { case 0: gen_sxth(tmp); break; @@ -10632,11 +10630,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 7: goto illegal_op; default: /* Saturate. */ - if (shift) { - if (op & 1) - tcg_gen_sari_i32(tmp, tmp, shift); - else - tcg_gen_shli_i32(tmp, tmp, shift); + if (op & 1) { + tcg_gen_sari_i32(tmp, tmp, shift); + } else { + tcg_gen_shli_i32(tmp, tmp, shift); } tmp2 = tcg_const_i32(imm); if (op & 4) { @@ -10827,9 +10824,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } tmp = load_reg(s, rm); - if (shift) { - tcg_gen_shli_i32(tmp, tmp, shift); - } + tcg_gen_shli_i32(tmp, tmp, shift); tcg_gen_add_i32(addr, addr, tmp); tcg_temp_free_i32(tmp); break;