[v3,30/34] target/arm: Update regime_is_user for EL2&0

Message ID	20190803184800.8221-31-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Sat, 3 Aug 2019 11:47:56 -0700 Message-Id: <20190803184800.8221-31-richard.henderson@linaro.org> In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org> References: <20190803184800.8221-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v3 30/34] target/arm: Update regime_is_user for EL2&0 Precedence: list Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Implement ARMv8.1-VHE \| expand [v3,00/34] target/arm: Implement ARMv8.1-VHE [v3,01/34] cputlb: Add tlb_set_asid_for_mmuidx [v3,02/34] cputlb: Add tlb_flush_asid_by_mmuidx and friends [v3,03/34] target/arm: Install ASIDs for long-form from EL1 [v3,04/34] target/arm: Install ASIDs for short-form from EL1 [v3,05/34] target/arm: Install ASIDs for EL2 [v3,06/34] target/arm: Define isar_feature_aa64_vh [v3,07/34] target/arm: Enable HCR_E2H for VHE [v3,08/34] target/arm: Add CONTEXTIDR_EL2 [v3,09/34] target/arm: Add TTBR1_EL2 [v3,10/34] target/arm: Update CNTVCT_EL0 for VHE [v3,11/34] target/arm: Add the hypervisor virtual counter [v3,12/34] target/arm: Add VHE system register redirection and aliasing [v3,13/34] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask [v3,14/34] target/arm: Simplify tlb_force_broadcast alternatives [v3,15/34] target/arm: Rename ARMMMUIdx_S12NSE to ARMMMUIdx_E10_ [v3,16/34] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 [v3,17/34] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* [v3,18/34] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE* [v3,19/34] target/arm: Rename ARMMMUIdx_S1E3 to ARMMMUIdx_SE3 [v3,20/34] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 [v3,21/34] target/arm: Reorganize ARMMMUIdx [v3,22/34] target/arm: Add regime_has_2_ranges [v3,23/34] target/arm: Update arm_mmu_idx for VHE [v3,24/34] target/arm: Update arm_sctlr for VHE [v3,25/34] target/arm: Update aa64_zva_access for EL2 [v3,26/34] target/arm: Update ctr_el0_access for EL2 [v3,27/34] target/arm: Install asids for E2&0 translation regime [v3,28/34] target/arm: Flush tlbs for E2&0 translation regime [v3,29/34] target/arm: Update arm_phys_excp_target_el for TGE [v3,30/34] target/arm: Update regime_is_user for EL2&0 [v3,31/34] target/arm: Update {fp, sve}_exception_el for VHE [v3,32/34] target/arm: Enable ARMv8.1-VHE in -cpu max [v3,33/34] target/arm: check TGE and E2H flags for EL0 pauth traps [v3,34/34] target/arm: generate a custom MIDR for -cpu max

Message ID

20190803184800.8221-31-richard.henderson@linaro.org

State

New

Headers

Received-SPF: pass (google.com: domain of
	qemu-devel-bounces+patch=linaro.org@nongnu.org designates
	209.51.188.17 as permitted sender) client-ip=209.51.188.17; 
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Sat,  3 Aug 2019 11:47:56 -0700
Message-Id: <20190803184800.8221-31-richard.henderson@linaro.org>
In-Reply-To: <20190803184800.8221-1-richard.henderson@linaro.org>
References: <20190803184800.8221-1-richard.henderson@linaro.org>
Subject: [Qemu-devel] [PATCH v3 30/34] target/arm: Update regime_is_user for
	EL2&0
Precedence: list
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

target/arm: Implement ARMv8.1-VHE | expand

Commit Message

Richard Henderson Aug. 3, 2019, 6:47 p.m. UTC

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/helper.c | 1 +
 1 file changed, 1 insertion(+)

-- 
2.17.1

diff --git a/target/arm/helper.c b/target/arm/helper.c
index a0969b78bf..d481716b97 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8936,6 +8936,7 @@  static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
 {
     switch (mmu_idx) {
     case ARMMMUIdx_SE0:
+    case ARMMMUIdx_EL20_0:
     case ARMMMUIdx_Stage1_E0:
     case ARMMMUIdx_MUser:
     case ARMMMUIdx_MSUser:

[v3,30/34] target/arm: Update regime_is_user for EL2&0

Commit Message

Patch