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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id g4sm84054164pfo.93.2019.07.31.13.38.44 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Wed, 31 Jul 2019 13:38:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 31 Jul 2019 13:38:06 -0700 Message-Id: <20190731203813.30765-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190731203813.30765-1-richard.henderson@linaro.org> References: <20190731203813.30765-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v2 25/32] target/arm: Install asids for E2&0 translation regime X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When clearing HCR_E2H, this involves re-installing the EL1&0 asid. Signed-off-by: Richard Henderson --- target/arm/helper.c | 38 ++++++++++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 2883d6e568..30f93f4792 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3518,10 +3518,29 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, } } +static void update_el2_asid(CPUARMState *env) +{ + CPUState *cs = env_cpu(env); + uint64_t ttbr0, ttbr1, ttcr; + int asid, idxmask; + + ttbr0 = env->cp15.ttbr0_el[2]; + ttbr1 = env->cp15.ttbr1_el[2]; + ttcr = env->cp15.tcr_el[2].raw_tcr; + idxmask = ARMMMUIdxBit_EL20_2 | ARMMMUIdxBit_EL20_0; + asid = extract64(ttcr & TTBCR_A1 ? ttbr1 : ttbr0, 48, 16); + + tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0); +} + static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { raw_write(env, ri, value); + if (arm_hcr_el2_eff(env) & HCR_E2H) { + /* We are running with EL2&0 regime and the ASID is active. */ + update_el2_asid(env); + } } static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4654,6 +4673,7 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) ARMCPU *cpu = env_archcpu(env); /* Begin with bits defined in base ARMv8.0. */ uint64_t valid_mask = MAKE_64BIT_MASK(0, 34); + uint64_t old_value; if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &= ~HCR_HCD; @@ -4680,15 +4700,25 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* Clear RES0 bits. */ value &= valid_mask; - /* These bits change the MMU setup: + old_value = env->cp15.hcr_el2; + env->cp15.hcr_el2 = value; + + /* + * These bits change the MMU setup: * HCR_VM enables stage 2 translation * HCR_PTW forbids certain page-table setups - * HCR_DC Disables stage1 and enables stage2 translation + * HCR_DC disables stage1 and enables stage2 translation + * HCR_E2H enables E2&0 translation regime. */ - if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { + if ((old_value ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_E2H)) { tlb_flush(CPU(cpu)); + /* Also install the correct ASID for the regime. */ + if (value & HCR_E2H) { + update_el2_asid(env); + } else { + update_lpae_el1_asid(env, false); + } } - env->cp15.hcr_el2 = value; /* * Updates to VI and VF require us to update the status of