From patchwork Wed Jul 31 20:38:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 170264 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp4479821ile; Wed, 31 Jul 2019 13:50:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqwgmjd/brvQtWlxiBUVm13fnsCFOIr2htt6acLIjODyxL+LT094EhYEzYLupmsCKyp/oAWC X-Received: by 2002:a67:a44b:: with SMTP id p11mr75240812vsh.237.1564606218465; Wed, 31 Jul 2019 13:50:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564606218; cv=none; d=google.com; s=arc-20160816; b=oncnDBjZSGybktpXdJI30lnTKb2Ma8tbQdXRXmdK/FKQUYXZ9LCpufa9wTwHZWN2l3 f0KwCkQuhfGp7SkU4aHvqpEpwNuE1hOqwrcOeknuCDYjF1u2PtR2P9dMLIldCEVGZzej +elQBPOTuhilWpmGKANzLcn8a35IGLjIfjjPOPtxd4VPFItIX4+F94CIcUXRQoQzt2Oz 8eEJeziCkj62nbctLXgA3hKxaCfMKdKkAEaF3NJdu2/f4+DkeIxCzfc0KTpzisBwcSwo l90R2WtXmMo3XF5Iz1On+rbVuy+dd5xYNed1maFv23yti8nPOAFFSMwRBYTKjYouzhvF NC6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=gkdd1xo9dAf4K2ZLEThkLYxs4H8KbbboSDJfUHi98zc=; b=YoYCCGqs8/Y8JTYtpfiK6xfuuRRlzPU7FQnmKuR2ZrNcNSRD5Tz/c4+pZrDhbL2W/7 Mn9bFuScP0sP8UitLtJuX0Ir3Pvwf1w8iBE5Q834uMlpcwShfta9w7KjdzeZRYhut93H KfFput5RUNewBqJjzd3k/uSPNlU0OnHrCgjGMRp5XaAqMTFFnFD8rBDI83XJvlaZrsR8 rdRJxjjqedJGl/iPnNuTw048dVouiBwoW082udnWu6XJhNAlKwb+Qqt2Z3eGCZnXrjjq VOtSK61HKCV5OWTwbpO2hPS19A+9Q3HSALmM0DH3PCkW+4LgFnDMwPA5qMaDfSwfXyJ5 4veg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZDbaISIZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m135si16366656vkd.93.2019.07.31.13.50.18 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jul 2019 13:50:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZDbaISIZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44458 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hsvY9-0004ha-Vy for patch@linaro.org; Wed, 31 Jul 2019 16:50:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32955) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hsvN0-0005IS-8y for qemu-devel@nongnu.org; Wed, 31 Jul 2019 16:38:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hsvMz-0003ew-2s for qemu-devel@nongnu.org; Wed, 31 Jul 2019 16:38:46 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:35141) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hsvMy-0003dv-Sv for qemu-devel@nongnu.org; Wed, 31 Jul 2019 16:38:45 -0400 Received: by mail-pg1-x543.google.com with SMTP id s1so26341816pgr.2 for ; Wed, 31 Jul 2019 13:38:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gkdd1xo9dAf4K2ZLEThkLYxs4H8KbbboSDJfUHi98zc=; b=ZDbaISIZ3zgNqxZlEnpBUY3V2zdR9HW9CR1WHtGeWAaHAYFzmG1zEiUvprFlqdWgBF OoDezKag3b/3idd6mx+ISvn38e2INhCTTjhgRgA+fb6OzEVxk99vZjc/n6f2Fkrtt4MP NdvOAY9UqpPnTLAdnqnZmP01d4tCo5Nr8TW04LgZrHetRTTiu8Xjt6e2i9kNZVlrDjRp QaxgMB3oG/u5BZp4G516V1v9Mh3ICvJJQTvv3F4m1EQn/ME1w9Cxsl83+cUjn0UQJEIu U0hyfSgyExKgrah2yP6hc33PXurZbRsvoO3umB0UXjfv16/TJZde8QSaqIVi5NEce9Wb HZEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gkdd1xo9dAf4K2ZLEThkLYxs4H8KbbboSDJfUHi98zc=; b=fFFiS1cA+ay5rCVVuyivg9qF+oPFukDNGwcpvy3GfC5TzRXSvWPtROEOv2vGVJAF7K 0a8KVq0A5jcfVN5cTN8LPXKSU6HIUR6sReuYYWggcLH7OWT3KjM/OBd2BQWHq7Jy3tTQ bBY4I4lgikry5ZSNH056J1Pvj+o0gvRYRBKYwlFtxVUeaejA5fId49eEMB4WDVyTDYz3 TJW2hfvOh493kdUv6ncfDR1v+mC3jlH0LuaAHN9Hjn6twjQGSBaRFVym2Ym4gvx2UW2I lfaGe21swmVHzyPIU9GbDbE4ik4IfpK5w3EC892KybVytEQmHdsomm14V2exz5rs+8tk KQUA== X-Gm-Message-State: APjAAAXVPUve9OB2JLk0oxR62ki/wpbilpBONTXcxTIqTp8aMH4q1rfk WJxXLslL/x783Kj5Aj/SDn35pw29BIw= X-Received: by 2002:a62:198d:: with SMTP id 135mr48906850pfz.169.1564605523502; Wed, 31 Jul 2019 13:38:43 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id g4sm84054164pfo.93.2019.07.31.13.38.42 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Wed, 31 Jul 2019 13:38:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 31 Jul 2019 13:38:04 -0700 Message-Id: <20190731203813.30765-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190731203813.30765-1-richard.henderson@linaro.org> References: <20190731203813.30765-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v2 23/32] target/arm: Update arm_mmu_idx for VHE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This covers initial generation in arm_mmu_idx, and reconstruction in core_to_arm_mmu_idx. As a conseqeuence, we also need a bit in TBFLAGS in order to make the latter reliable. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 42 +++++++++++++++++++++++++++++++----------- 2 files changed, 33 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b5300f9014..64cda8dbea 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3153,6 +3153,8 @@ FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) +/* For A profile only, if EL2 is AA64 and HCR_EL2.E2H is set. */ +FIELD(TBFLAG_ANY, E2H, 22, 1) /* Bit usage when in AArch32 state: */ FIELD(TBFLAG_A32, THUMB, 0, 1) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5472424179..578dcfefbf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11257,21 +11257,29 @@ int fp_exception_el(CPUARMState *env, int cur_el) ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx) { + bool e2h; + if (arm_feature(env, ARM_FEATURE_M)) { return mmu_idx | ARM_MMU_IDX_M; } mmu_idx |= ARM_MMU_IDX_A; + if (mmu_idx & ARM_MMU_IDX_S) { + return mmu_idx; + } + + e2h = (env->cp15.hcr_el2 & HCR_E2H) != 0; + if (!arm_el_is_aa64(env, 2)) { + e2h = false; + } + switch (mmu_idx) { case 0 | ARM_MMU_IDX_A: - return ARMMMUIdx_EL10_0; + return e2h ? ARMMMUIdx_EL20_0 : ARMMMUIdx_EL10_0; case 1 | ARM_MMU_IDX_A: return ARMMMUIdx_EL10_1; case ARMMMUIdx_E2: - case ARMMMUIdx_SE0: - case ARMMMUIdx_SE1: - case ARMMMUIdx_SE3: - return mmu_idx; + return e2h ? ARMMMUIdx_EL20_2 : ARMMMUIdx_E2; default: g_assert_not_reached(); } @@ -11299,24 +11307,28 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) ARMMMUIdx arm_mmu_idx(CPUARMState *env) { + bool e2h, sec; int el; if (arm_feature(env, ARM_FEATURE_M)) { return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); } + sec = arm_is_secure_below_el3(env); + e2h = (env->cp15.hcr_el2 & HCR_E2H) != 0; + if (!arm_el_is_aa64(env, 2)) { + e2h = false; + } + el = arm_current_el(env); switch (el) { case 0: - /* TODO: ARMv8.1-VHE */ + return sec ? ARMMMUIdx_SE0 : e2h ? ARMMMUIdx_EL20_0 : ARMMMUIdx_EL10_0; case 1: - return (arm_is_secure_below_el3(env) - ? ARMMMUIdx_SE0 + el - : ARMMMUIdx_EL10_0 + el); + return sec ? ARMMMUIdx_SE1 : ARMMMUIdx_EL10_1; case 2: - /* TODO: ARMv8.1-VHE */ /* TODO: ARMv8.4-SecEL2 */ - return ARMMMUIdx_E2; + return e2h ? ARMMMUIdx_EL20_2 : ARMMMUIdx_E2; case 3: return ARMMMUIdx_SE3; default: @@ -11428,6 +11440,14 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); + /* + * Include E2H in TBFLAGS so that core_to_arm_mmu_idx can + * reliably determine E1&0 vs E2&0 regimes. + */ + if (arm_el_is_aa64(env, 2) && (env->cp15.hcr_el2 & HCR_E2H)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, E2H, 1); + } + /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine * states defined in the ARM ARM for software singlestep: * SS_ACTIVE PSTATE.SS State