From patchwork Fri Jul 26 17:49:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169869 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp354496ilk; Fri, 26 Jul 2019 10:52:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqzhrOGmsRO8mZJQuQv/u1VLFdSswiB3IIdkLb9YO51DU7Z8fu0STlyGrfoo3SxUdWuBM2mQ X-Received: by 2002:a17:906:b34d:: with SMTP id cd13mr73581674ejb.107.1564163524681; Fri, 26 Jul 2019 10:52:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163524; cv=none; d=google.com; s=arc-20160816; b=FvUBctx4EkrCuk7EZJ/9Ggqkf7jBt+AiH1MEdiqanTITIH8atsQ8upSGB0Tfyeo3eW 4E6YZJO3RN8J1PAL0/BvJleEQsL1ao3J+vifE4bisGQRQZEtZLIQajgAdY0eTA0T3CLZ oSfmW9Npey0pmpB+c68f3cNw4vXKscxXN2VoaBkASgDuvWb60dDid60Z7Q2aNiQtcBrt zDu8/3sOXbyBq1d0kay5TDv9akuFEfwbDUZEQoyohdJ8yIZ7AfGFvXMeYRbgLvMXQUxp EX3oBMC3m9rY6ZPTSYEPazewdp+FMRW8PRhunNYSFt90KW18FqT9u24pnBDhWrajCrWd Vr6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=7qMkBV6xIInqYLHQbsNGGIckvY18Pfy+zYd9EjT4q5E=; b=ZYw3MStuF7lBlKA3bN2PenKPtuEqN0qgwnAXawx6brQR429EBhfUZNLtfzzfneJfGn jSjXUdRWVAxXXtiOs80Asbn5Bh9hLrkG7iRlJPRgQ5TKNWm/z9JnLShWhvHowwOCEuN6 0wOuQ1w9x75Ix0A9y36dC8ywZWVKD9Th1aJQpCTj4Ft6IR1b2N8ljnFwzE66/36eJh7d 8J6+4wlhRkowpKWmNiGFmPQedyPaPywnI2HMjh15FR5mr9mdKMzN10jdvaBn9h3DkOh5 gCfnJqS7ix+Dm8M5eOLoXBHaRNDudN+oYvW5Nc/BEs2JkrCuxNcO4Q7+aPS/9HvNnXIB Crsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HsnHg8Za; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t2si13362999edq.237.2019.07.26.10.52.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:52:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HsnHg8Za; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42202 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nu-0005zX-MD for patch@linaro.org; Fri, 26 Jul 2019 13:52:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57076) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mc-0001mQ-Tj for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mb-0007Me-RM for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:42 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:38137) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mb-0007LC-Ln for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:41 -0400 Received: by mail-pl1-x644.google.com with SMTP id az7so25001434plb.5 for ; Fri, 26 Jul 2019 10:50:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7qMkBV6xIInqYLHQbsNGGIckvY18Pfy+zYd9EjT4q5E=; b=HsnHg8ZaUxSGLCpbuDc4pmqUNrk330qSqmCO7NJTJx3m/vp85OhDyq2sIfoOQMvEbC zwJTp6aCdSb8Vzb5I3MzM/8NsArcdkXmTDaputpA722tHqznS9eORwuHooib+qqP6QPX i4jgNJnIHUVe00Xv060oFeiZXLFCKKhZWa5JReNbzYgaAUay+JlIWvlmRee4OYAushcY 4plOVDzEuzXkEswad/+xa69p7Z7piLmNqV87qxYkjE+jbdyvH9bjbZxUdW5Y5JYhJ+3Y kEciIOkrHb7VL37Qaa59SQ0V+Er9+A7aybjUXqZYyK8jIcVNVueuEv6o3qiwkRkNOKkv wNmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7qMkBV6xIInqYLHQbsNGGIckvY18Pfy+zYd9EjT4q5E=; b=Myr/zzSA4NqkVChSo8NuqX9ct8Ff6dxoBjTt49ei+Xe3pVPBgfABOq40dhFcAWrTVj Pea5JmwdfKFXK19jQ5ekTPYmpuZ70E4kFNyZwZhsrWflSL/h1kJpo25u89tspI1GrCUl 2U116H9I76FGyGgJbi5h8cxsGkDo5SL0FJ3AfBryG3F4bek27dleUN8vjUI6e7ocpmaa 017kzFnjOp2yu2+9J3W16bTT6avrQjNz70Cui46ydJR14Tcfcy2DnJBaaG0vtacU8JUT cLcPY4INIfZn2JpZqn6W4VI0eKXgl2d3Ez6MEfjafJrzT3Yb/u10DzIbIXfzfdw/KvHv mP0g== X-Gm-Message-State: APjAAAU2rKZseSAH0O2scxPtUJkV4tAIfxkR0iodlgJrZx3qWZ5ZLm7n UYPtOxZpqrX44eBbA4qgSqzMXH87DdI= X-Received: by 2002:a17:902:4201:: with SMTP id g1mr97729634pld.300.1564163440520; Fri, 26 Jul 2019 10:50:40 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.39 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:30 -0700 Message-Id: <20190726175032.6769-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 05/67] target/arm: Use the saved value of the insn address X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The address of the current insn is still available in s->base.pc_next, and need not be recomputed from s->pc - 4. Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 0848fb933a..595385e1b1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1212,7 +1212,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) * as an undefined insn by runtime configuration (ie before * the insn really executes). */ - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); gen_helper_pre_hvc(cpu_env); /* Otherwise we will treat this as a real exception which * happens after execution of the insn. (The distinction matters @@ -1231,7 +1231,7 @@ static inline void gen_smc(DisasContext *s) */ TCGv_i32 tmp; - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); tmp = tcg_const_i32(syn_aa32_smc()); gen_helper_pre_smc(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -3190,7 +3190,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) /* Sync state because msr_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); tcg_reg = load_reg(s, rn); tcg_tgtmode = tcg_const_i32(tgtmode); tcg_regno = tcg_const_i32(regno); @@ -3212,7 +3212,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) /* Sync state because mrs_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); tcg_reg = tcg_temp_new_i32(); tcg_tgtmode = tcg_const_i32(tgtmode); tcg_regno = tcg_const_i32(regno); @@ -7219,7 +7219,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); tmpptr = tcg_const_ptr(ri); tcg_syn = tcg_const_i32(syndrome); tcg_isread = tcg_const_i32(isread); @@ -7629,7 +7629,7 @@ static void gen_srs(DisasContext *s, tmp = tcg_const_i32(mode); /* get_r13_banked() will raise an exception if called from System mode */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); gen_helper_get_r13_banked(addr, cpu_env, tmp); tcg_temp_free_i32(tmp); switch (amode) {