[47/67] target/arm: Convert T16 add pc/sp (immediate)

Message ID	20190726175032.6769-48-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:12 -0700 Message-Id: <20190726175032.6769-48-richard.henderson@linaro.org> In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH 47/67] target/arm: Convert T16 add pc/sp (immediate) Precedence: list Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	target/arm: Convert aa32 base isa to decodetree \| expand [00/67] target/arm: Convert aa32 base isa to decodetree [01/67] decodetree: Allow !function with no input bits [02/67] target/arm: Remove offset argument to gen_exception_insn [03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn [04/67] target/arm: Remove offset argument to gen_exception_internal_insn [05/67] target/arm: Use the saved value of the insn address [06/67] target/arm: Introduce pc_read [07/67] target/arm: Introduce add_reg_for_lit [08/67] target/arm: Use store_reg_from_load in thumb2 code [09/67] target/arm: Fold a pc load into load_reg [10/67] target/arm: Move test for AL into arm_skip_unless [11/67] target/arm: Add stubs for aa32 decodetree [12/67] target/arm: Introduce gen_illegal_op [13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm) [14/67] target/arm: Convert multiply and multiply accumulate [15/67] target/arm: Convert Saturating addition and subtraction [16/67] target/arm: Convert Halfword multiply and multiply accumulate [17/67] target/arm: Convert MSR (immediate) and hints [18/67] target/arm: Convert MRS/MSR (banked, register) [19/67] target/arm: Convert Cyclic Redundancy Check [20/67] target/arm: Convert the rest of A32 Miscelaneous instructions [21/67] target/arm: Convert T32 ADDW/SUBW [22/67] target/arm: Convert load/store (register, immediate, literal) [23/67] target/arm: Convert Synchronization primitives [24/67] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF [25/67] target/arm: Convert Parallel addition and subtraction [26/67] target/arm: Convert Packing, unpacking, saturation, and reversal [27/67] target/arm: Convert Signed multiply, signed and unsigned divide [28/67] target/arm: Convert MOVW, MOVT [29/67] target/arm: Convert LDM, STM [30/67] target/arm: Convert B, BL, BLX (immediate) [31/67] target/arm: Convert SVC [32/67] target/arm: Convert RFE and SRS [33/67] target/arm: Convert Clear-Exclusive, Barriers [34/67] target/arm: Convert CPS (privileged) [35/67] target/arm: Convert SETEND [36/67] target/arm: Convert PLI, PLD, PLDW [37/67] target/arm: Convert Unallocated memory hint [38/67] target/arm: Convert Table Branch [39/67] target/arm: Convert SG [40/67] target/arm: Convert TT [41/67] target/arm: Simplify disas_thumb2_insn [42/67] target/arm: Simplify disas_arm_insn [43/67] target/arm: Add skeleton for T16 decodetree [44/67] target/arm: Convert T16 data-processing (two low regs) [45/67] target/arm: Convert T16 load/store (register offset) [46/67] target/arm: Convert T16 load/store (immediate offset) [47/67] target/arm: Convert T16 add pc/sp (immediate) [48/67] target/arm: Convert T16 load/store multiple [49/67] target/arm: Convert T16 add/sub (3 low, 2 low and imm) [50/67] target/arm: Convert T16 one low register and immediate [51/67] target/arm: Convert T16 branch and exchange [52/67] target/arm: Convert T16 add, compare, move (two high registers) [53/67] target/arm: Convert T16 adjust sp (immediate) [54/67] target/arm: Convert T16, extract [55/67] target/arm: Convert T16, Change processor state [56/67] target/arm: Convert T16, Reverse bytes [57/67] target/arm: Convert T16, nop hints [58/67] target/arm: Convert T16, push and pop [59/67] target/arm: Convert T16, Conditional branches, Supervisor call [60/67] target/arm: Convert T16, Miscellaneous 16-bit instructions [61/67] target/arm: Convert T16, shift immediate [62/67] target/arm: Convert T16, load (literal) [63/67] target/arm: Convert T16, Unconditional branch [64/67] target/arm: Convert T16, long branches [65/67] target/arm: Clean up disas_thumb_insn [66/67] target/arm: Move singlestep check from gen_jmp to gen_goto_tb [67/67] target/arm: Merge gen_bx_im into trans_BLX_i

Message ID

20190726175032.6769-48-richard.henderson@linaro.org

State

Superseded

Headers

Received-SPF: pass (google.com: domain of
	qemu-devel-bounces+patch=linaro.org@nongnu.org designates
	209.51.188.17 as permitted sender) client-ip=209.51.188.17; 
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Fri, 26 Jul 2019 10:50:12 -0700
Message-Id: <20190726175032.6769-48-richard.henderson@linaro.org>
In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org>
References: <20190726175032.6769-1-richard.henderson@linaro.org>
Subject: [Qemu-devel] [PATCH 47/67] target/arm: Convert T16 add pc/sp
	(immediate)
Precedence: list
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org
Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org
Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>

Series

target/arm: Convert aa32 base isa to decodetree | expand

Commit Message

Richard Henderson July 26, 2019, 5:50 p.m. UTC

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/translate.c | 12 +-----------
 target/arm/t16.decode  |  7 +++++++
 2 files changed, 8 insertions(+), 11 deletions(-)

-- 
2.17.1

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 28f274ca7c..525276ed13 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10758,19 +10758,9 @@  static void disas_thumb_insn(DisasContext *s, uint32_t insn)
     case 7: /* load/store byte immediate offset, in decodetree */
     case 8: /* load/store halfword immediate offset, in decodetree */
     case 9: /* load/store from stack, in decodetree */
+    case 10: /* add PC/SP (immediate), in decodetree */
         goto illegal_op;
 
-    case 10:
-        /*
-         * 0b1010_xxxx_xxxx_xxxx
-         *  - Add PC/SP (immediate)
-         */
-        rd = (insn >> 8) & 7;
-        val = (insn & 0xff) * 4;
-        tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val);
-        store_reg(s, rd, tmp);
-        break;
-
     case 11:
         /* misc */
         op = (insn >> 8) & 0xf;
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 797e4e7068..568656ecd6 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -23,6 +23,7 @@ 
 &s_rrr_shr       !extern s rn rd rm rs shty
 &s_rri_rot       !extern s rn rd imm rot
 &s_rrrr          !extern s rd rn rm ra
+&ri              !extern rd imm
 &ldst_rr         !extern p w u rn rt rm shimm shtype
 &ldst_ri         !extern p w u rn rt imm
 
@@ -102,3 +103,9 @@  LDRH_ri         10001 ..... ... ...             @ldst_ri_2
 
 STR_ri          10010 ... ........              @ldst_spec_i rn=13
 LDR_ri          10011 ... ........              @ldst_spec_i rn=13
+
+# Add PC/SP (immediate)
+
+ADR             10100 rd:3 ........             imm=%imm8_0x4
+ADD_rri         10101 rd:3 ........ \
+                &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4  # SP

[47/67] target/arm: Convert T16 add pc/sp (immediate)

Commit Message

Patch