From patchwork Fri Jul 26 17:50:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169893 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp359611ilk; Fri, 26 Jul 2019 10:57:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqwwV4vt6JAJRK47XCzvyaE9T2BC66IeU4fOx6IENas5lU3vVJGBpUqLnIghG9i8AHL+nLnJ X-Received: by 2002:a50:eb0b:: with SMTP id y11mr83840193edp.224.1564163848358; Fri, 26 Jul 2019 10:57:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163848; cv=none; d=google.com; s=arc-20160816; b=gPom2JHqcY5RvCXVUr5qphmVNGbsdqCHxuDsdzNNxOZfWkSWIGlRy9ouSd3juomefW +ugcuqWq1Xr+a5AB7F0zP+riVVJa8CR1BAVJbS0v/vXaL7mb2axyYqe47er50qbARBCL nQbC7Iix4BMqD6gE8m6vjxXbiWQ8EIuEy5hFj7AcH6CA47te8nzSW2AMaSnlUYvHGUaI cKWS5yrz3ZT5Po8CEHhq9Kp9EgZu3nNuSfRpYfKhKEwd3jehy9nW7dI5zTBronSA+jFu +q+6XvNQpLqQmvgQmH+mQtGdW/kEzN82v/1T1xKBx5umD+i9gw2GrEr+cnNylbTkRN+E oG/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=rYLqZpflL8enArleH0yr8+1WjHV+ohzdNCLhPhFauU8=; b=O7vaXOFNfJKPRKa/soRaYihQ/UJx0SaltoZRPl86DdiIFhoXn3ET8oX4dqHejDRrx8 3Z4fFV5HWDPoDaXfabz6JVig1Fzu4+DiganFBO6NMaJ3NEtvu3113sePeNDskIzX8oXj 3laanILXIRVlpgtvkVvh++x8tdI/Ei2uT/yDdUZV9KUcuctKRNzi6ee7SQoE87DcSwd7 URJK6lz9lH8clvbZaQGL1A/MOZqhffIb1NkjAxYUk7x8LYzY0cF9g960kKdqxoqV6fPL grzVRckYTm9OHUZdrP5PEEAICCKcY8qq7RYMKArLHaE8FFFBoiyqYJtB5BUoI/tD0TuF ou8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vUuFxnGZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d24si11658479ejt.166.2019.07.26.10.57.28 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:57:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vUuFxnGZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42442 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4T7-0004xb-U7 for patch@linaro.org; Fri, 26 Jul 2019 13:57:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59049) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NW-0005fG-Bq for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NR-0000sI-SQ for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:36 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:39973) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NR-0000lc-Js for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:33 -0400 Received: by mail-pg1-x541.google.com with SMTP id w10so25118876pgj.7 for ; Fri, 26 Jul 2019 10:51:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rYLqZpflL8enArleH0yr8+1WjHV+ohzdNCLhPhFauU8=; b=vUuFxnGZfQO+eydHDnu89G4IdZjWb7HlKZY0QaHpGWE2BItOyaXMRIyVdYMQ5FlbEM Yim3sn4LSJI+5S27aQP1J2C2gp1832rmmjn9LZEPvvc6vHBj15SNzxQnSTccj6It2Qu6 cS6QTKFPWIY1IProfCj0G52h3yThcb54AOYaoXea967IO0U7De6pKTx3WjHAbiwNNoQW Pv2eBFF0vGE0C8m5ue1r55cJDh1mazO5ejuFcwKyH0XSM6zu9//T4NI/KhOvRakQY0bv LIsUPxvbl/VsMzZRVQY/gHNa2DNFyrVkYn/6y36PZCjMoYP7ouD3kNNyjtf9KLKQhUlg STGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rYLqZpflL8enArleH0yr8+1WjHV+ohzdNCLhPhFauU8=; b=t6eSJVZ9WBeYqG7QFh0GjW0PLsjEM/XSlrM0IQY9O6nq5ax8WOX5M+vRPtg+IgWOht T8jBV0KaAd4fHIXU2lG4NClBacLqIi982PDlS1gQqn+b4h3kh8fYONmCRT6tL1a6ZNH+ zqPSxXjYoIKh0y9Q44d/L/DpLR2kbH7MNGiSEYFrk/n0zukDRtllJhI5EMmxaWGud60r pJKfjntUMnyXCZoZrTboDxJzeGl/51avPhUSsSYSaKWSLBhSr5Ox8K2dSiU9cehym3gq BxqmfFvVKlNT5xm9b+Xp7yGxff2JH4MXjNDoQp/vj+6r3bsEsxyZdZyxiCVvbDRHZ6hu uuRw== X-Gm-Message-State: APjAAAVqb4Z28vN79tdSyBlW8YvusFMpAIQ9KdNyPsvYyKbQ5HbFGmqA 3MUnlbXDPlVe/13BnqHDIHXntFmXbQI= X-Received: by 2002:a63:7e1d:: with SMTP id z29mr92318259pgc.346.1564163490363; Fri, 26 Jul 2019 10:51:30 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.29 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:11 -0700 Message-Id: <20190726175032.6769-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 46/67] target/arm: Convert T16 load/store (immediate offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 94 +++--------------------------------------- target/arm/t16.decode | 33 +++++++++++++++ 2 files changed, 38 insertions(+), 89 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 7b87621315..28f274ca7c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10753,97 +10753,13 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) */ goto illegal_op; - case 5: - /* load/store register offset, in decodetree */ + case 5: /* load/store register offset, in decodetree */ + case 6: /* load/store word immediate offset, in decodetree */ + case 7: /* load/store byte immediate offset, in decodetree */ + case 8: /* load/store halfword immediate offset, in decodetree */ + case 9: /* load/store from stack, in decodetree */ goto illegal_op; - case 6: - /* load/store word immediate offset */ - rd = insn & 7; - rn = (insn >> 3) & 7; - addr = load_reg(s, rn); - val = (insn >> 4) & 0x7c; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 7: - /* load/store byte immediate offset */ - rd = insn & 7; - rn = (insn >> 3) & 7; - addr = load_reg(s, rn); - val = (insn >> 6) & 0x1f; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 8: - /* load/store halfword immediate offset */ - rd = insn & 7; - rn = (insn >> 3) & 7; - addr = load_reg(s, rn); - val = (insn >> 5) & 0x3e; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 9: - /* load/store from stack */ - rd = (insn >> 8) & 7; - addr = load_reg(s, 13); - val = (insn & 0xff) * 4; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - case 10: /* * 0b1010_xxxx_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 567c5005d6..797e4e7068 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -69,3 +70,35 @@ LDR_rr 0101 100 ... ... ... @ldst_rr LDRH_rr 0101 101 ... ... ... @ldst_rr LDRB_rr 0101 110 ... ... ... @ldst_rr LDRSH_rr 0101 111 ... ... ... @ldst_rr + +# Load/store word/byte (immediate offset) + +%imm5_6x4 6:5 !function=times_4 + +@ldst_ri_1 ..... imm:5 rn:3 rt:3 \ + &ldst_ri p=1 w=0 u=1 +@ldst_ri_4 ..... ..... rn:3 rt:3 \ + &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4 + +STR_ri 01100 ..... ... ... @ldst_ri_4 +LDR_ri 01101 ..... ... ... @ldst_ri_4 +STRB_ri 01110 ..... ... ... @ldst_ri_1 +LDRB_ri 01111 ..... ... ... @ldst_ri_1 + +# Load/store halfword (immediate offset) + +%imm5_6x2 6:5 !function=times_2 +@ldst_ri_2 ..... ..... rn:3 rt:3 \ + &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2 + +STRH_ri 10000 ..... ... ... @ldst_ri_2 +LDRH_ri 10001 ..... ... ... @ldst_ri_2 + +# Load/store (SP-relative) + +%imm8_0x4 0:8 !function=times_4 +@ldst_spec_i ..... rt:3 ........ \ + &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4 + +STR_ri 10010 ... ........ @ldst_spec_i rn=13 +LDR_ri 10011 ... ........ @ldst_spec_i rn=13